Tool VeriFuzz 1.0.0 CPAchecker 1.7-svn 29852 ULTIMATE Automizer 0.1.23-635dfa2a CPA-witness2test 1.7-svn 29852 CProver witness2test 0.1 CPAchecker 1.7-svn 29852 ULTIMATE Automizer 0.1.23-635dfa2a
Limits timelimit: 900 s, memlimit: 15000 MB, CPU core limit: 8 timelimit: 90 s, memlimit: 7000 MB, CPU core limit: 2 timelimit: 900 s, memlimit: 7000 MB, CPU core limit: 2
Host apollon*
OS Linux 4.15.0-42-generic
System CPU: Intel Xeon E3-1230 v5 @ 3.40 GHz, cores: 8, frequency: 3.8 GHz, Turbo Boost: disabled; RAM: 33546 MB
Date of execution 2018-12-09 02:47:33 CET 2018-12-09 17:43:44 CET 2018-12-09 18:26:53 CET 2018-12-09 18:31:36 CET 2018-12-12 22:04:17 CET 2018-12-09 17:35:51 CET 2018-12-09 18:23:50 CET
Run set verifuzz.sv-comp19_prop-reachsafety.ReachSafety-BitVectors cpa-seq-validate-violation-witnesses-verifuzz.sv-comp19_prop-reachsafety.ReachSafety-BitVectors uautomizer-validate-violation-witnesses-verifuzz.sv-comp19_prop-reachsafety.ReachSafety-BitVectors cpa-witness2test-validate-violation-witnesses-verifuzz.sv-comp19_prop-reachsafety.ReachSafety-BitVectors fshell-witness2test-validate-violation-witnesses-verifuzz.sv-comp19_prop-reachsafety.ReachSafety-BitVectors cpa-seq-validate-correctness-witnesses-verifuzz.sv-comp19_prop-reachsafety.ReachSafety-BitVectors uautomizer-validate-correctness-witnesses-verifuzz.sv-comp19_prop-reachsafety.ReachSafety-BitVectors
Options -witnessValidation -setprop witness.checkProgramHash=false -heap 5000m -benchmark -setprop cpa.predicate.memoryAllocationsAlwaysSucceed=true -setprop cpa.smg.memoryAllocationFunctions=malloc,__kmalloc,kmalloc,kzalloc,kzalloc_node,ldv_zalloc,ldv_malloc -setprop cpa.smg.arrayAllocationFunctions=calloc,kmalloc_array,kcalloc -setprop cpa.smg.zeroingMemoryAllocation=calloc,kzalloc,kcalloc,kzalloc_node,ldv_zalloc -setprop cpa.smg.deallocationFunctions=free,kfree,kfree_const -witness ../../results-verified/verifuzz.2018-12-09_0247.logfiles/${rundefinition_name}.${inputfile_name}.files/witness.graphml --full-output --validate ../../results-verified/verifuzz.2018-12-09_0247.logfiles/${rundefinition_name}.${inputfile_name}.files/witness.graphml -setprop witness.checkProgramHash=false -heap 5000m -benchmark -setprop analysis.summaryEdges=true -setprop cpa.callstack.skipVoidRecursion=true -setprop cpa.callstack.skipFunctionPointerRecursion=true -witness ../../results-verified/verifuzz.2018-12-09_0247.logfiles/${rundefinition_name}.${inputfile_name}.files/witness.graphml --graphml-witness ../../results-verified/verifuzz.2018-12-09_0247.logfiles/${rundefinition_name}.${inputfile_name}.files/witness.graphml -witnessValidation -setprop witness.checkProgramHash=false -heap 5000m -benchmark -setprop cpa.predicate.memoryAllocationsAlwaysSucceed=true -witness ../../results-verified/verifuzz.2018-12-09_0247.logfiles/${rundefinition_name}.${inputfile_name}.files/witness.graphml --full-output --validate ../../results-verified/verifuzz.2018-12-09_0247.logfiles/${rundefinition_name}.${inputfile_name}.files/witness.graphml
sv-benchmarks/c/ status score witness inspect witness cpu (s) wall (s) mem (MB) energy (J) blkio-w (MB) blkio-r (MB) status score witness inspect witness cpu (s) wall (s) mem (MB) energy blkio-w (MB) blkio-r (MB) status score witness inspect witness cpu (s) wall (s) mem (MB) energy blkio-w (MB) blkio-r (MB) status score witness inspect witness cpu (s) wall (s) mem (MB) energy blkio-w (MB) blkio-r (MB) status score witness inspect witness cpu (s) wall (s) mem (MB) energy blkio-w (MB) blkio-r (MB) status score witness inspect witness cpu (s) wall (s) mem (MB) energy blkio-w (MB) blkio-r (MB) status score witness inspect witness cpu (s) wall (s) mem (MB) energy blkio-w (MB) blkio-r (MB)
bitvector/byte_add_false-unreach-call_true-no-overflow_true-termination.i 1 4.2 2.5 160 43 .84 0      1 12    6.0  420 0   .0041 -32 7.1   4.0   300   .66 .0041 1 3.9  2.3  250 0   0      1 .60   .60   20    .057 0     - -
bitvector/sum02_false-unreach-call_true-no-overflow.i 1 12   10   150 150 .66 0      0 93    82    1500 0   .30   0 18     15     310   .62 0      1 3.5  2.1  250 0   0      1 .60   .60   20    .045 0     - -
bitvector/byte_add_1_true-unreach-call_true-no-overflow_true-termination.i 0 900   920   160 12000 .85 0      - - - - 0 .67 .41 40 0   0   0 .020 .020 5.6 0   0  
bitvector/byte_add_2_true-unreach-call_true-no-overflow_true-termination.i 0 900   920   160 11000 .72 0      - - - - 0 .73 .44 42 0   0   0 .020 .021 5.6 0   0  
bitvector/gcd_1_true-unreach-call_true-no-overflow.i 0 900   920   150 12000 .93 0      - - - - 0 .80 .50 40 0   0   0 .021 .022 5.6 0   0  
bitvector/gcd_2_true-unreach-call_true-no-overflow.i 0 900   920   150 12000 .79 .0041 - - - - 0 .71 .44 40 0   0   0 .020 .021 5.6 0   0  
bitvector/gcd_3_true-unreach-call_true-no-overflow.i 0 900   920   150 13000 .84 0      - - - - 0 .69 .43 42 0   0   0 .020 .022 5.6 0   0  
bitvector/gcd_4_true-unreach-call_true-no-overflow_true-termination.i 0 900   920   150 12000 .84 0      - - - - 0 .81 .48 40 0   0   0 .024 .025 5.5 0   0  
bitvector/interleave_bits_true-unreach-call_true-no-overflow.i 0 900   920   150 9900 .94 0      - - - - 0 .60 .37 40 0   0   0 .020 .021 5.6 0   0  
bitvector/jain_1_true-unreach-call_true-no-overflow_false-termination.i 0 870   880   170 9800 .61 0      - - - - 0 .59 .38 40 0   0   0 .020 .023 5.6 0   0  
bitvector/jain_2_true-unreach-call_true-no-overflow_false-termination.i 0 17   16   230 220 .37 49      - - - - 0 .66 .40 40 0   0   0 .019 .020 5.6 0   0  
bitvector/jain_4_true-unreach-call_true-no-overflow_false-termination.i 0 17   16   180 210 .37 0      - - - - 0 .71 .44 42 0   0   0 .020 .021 5.6 0   0  
bitvector/jain_5_true-unreach-call_true-no-overflow.i 0 53   52   150 580 .37 0      - - - - 0 .67 .42 41 0   0   0 .020 .021 5.6 0   0  
bitvector/jain_6_true-unreach-call_true-no-overflow_false-termination.i 0 17   16   180 230 .37 0      - - - - 0 .74 .45 42 0   0   0 .020 .020 5.6 0   0  
bitvector/jain_7_true-unreach-call_true-no-overflow_false-termination.i 0 17   16   180 200 .37 0      - - - - 0 .72 .44 41 0   0   0 .019 .020 5.6 0   0  
bitvector/modulus_true-unreach-call_true-no-overflow.i 0 900   920   200 11000 .62 45      - - - - 0 .63 .39 40 0   0   0 .021 .022 5.6 0   0  
bitvector/num_conversion_1_true-unreach-call_true-no-overflow.i 0 900   920   200 9800 .78 45      - - - - 0 .71 .43 41 0   0   0 .020 .021 5.6 0   0  
bitvector/num_conversion_2_true-unreach-call_true-no-overflow.i 0 900   920   160 10000 .79 .0041 - - - - 0 .60 .38 41 0   0   0 .020 .020 5.6 0   0  
bitvector/parity_true-unreach-call_true-no-overflow.i 0 900   920   160 12000 .84 0      - - - - 0 .82 .51 42 0   0   0 .019 .020 5.6 0   0  
bitvector/sum02_true-unreach-call_true-no-overflow.i 0 890   880   150 12000 .51 .0041 - - - - 0 .58 .36 40 0   0   0 .021 .022 5.6 0   0  
bitvector/s3_clnt_1_false-unreach-call_true-no-overflow.BV.c.cil.c 1 120   120   200 1500 .95 0      1 5.5  3.0  280 0   0      -32 8.2   4.6   310   .62 0      0 5.2  2.9  270 0   .041  1 .63   .63   20    .12  0     - -
bitvector/s3_clnt_2_false-unreach-call_true-no-overflow.BV.c.cil.c 1 140   140   200 1700 1.2  0      1 7.3  4.0  280 0   0      -32 8.1   5.0   310   .62 .041  1 5.3  2.9  270 0   .041  1 .64   .64   21    .11  .041 - -
bitvector/s3_clnt_3_false-unreach-call_true-no-overflow.BV.c.cil.c 1 56   55   200 700 .81 0      1 5.5  3.0  270 0   0      -32 8.1   4.9   310   .66 0      1 5.1  2.8  270 0   0      1 .63   .63   21    .11  0     - -
bitvector/s3_clnt_1_true-unreach-call_true-no-overflow.BV.c.cil.c 0 870   880   200 9400 .90 0      - - - - 0 .77 .47 40 0   0   0 .021 .021 5.6 0   0  
bitvector/s3_clnt_2_true-unreach-call_true-no-overflow.BV.c.cil.c 0 870   880   200 11000 1.2  0      - - - - 0 .72 .45 40 0   0   0 .019 .020 5.6 0   0  
bitvector/s3_clnt_3_true-unreach-call_true-no-overflow.BV.c.cil.c 0 870   880   200 11000 1.2  0      - - - - 0 .61 .36 41 0   0   0 .020 .021 5.6 0   0  
bitvector/s3_srvr_1_alt_true-unreach-call_true-no-overflow.BV.c.cil.c 0 860   880   210 12000 .83 0      - - - - 0 .68 .43 41 0   0   0 .019 .020 5.6 0   0  
bitvector/s3_srvr_1_true-unreach-call_true-no-overflow.BV.c.cil.c 0 870   880   210 12000 1.2  0      - - - - 0 .71 .44 40 0   0   0 .020 .020 5.6 0   0  
bitvector/s3_srvr_2_alt_true-unreach-call_true-no-overflow_false-termination.BV.c.cil.c 0 870   880   210 12000 2.6  0      - - - - 0 .78 .48 41 0   0   0 .020 .020 5.6 0   0  
bitvector/s3_srvr_2_true-unreach-call_true-no-overflow_false-termination.BV.c.cil.c 0 870   880   210 9500 2.5  0      - - - - 0 .75 .45 40 0   0   0 .021 .021 5.6 0   0  
bitvector/s3_srvr_3_alt_true-unreach-call_true-no-overflow.BV.c.cil.c 0 870   880   210 11000 1.3  0      - - - - 0 .77 .46 42 0   0   0 .021 .021 5.6 0   0  
bitvector/s3_srvr_3_true-unreach-call_true-no-overflow.BV.c.cil.c 0 870   880   210 11000 1.2  0      - - - - 0 .72 .44 41 0   0   0 .020 .021 5.6 0   0  
bitvector/soft_float_1_true-unreach-call_true-no-overflow_true-termination.c.cil.c 0 870   880   160 12000 .57 0      - - - - 0 .58 .39 40 0   0   0 .020 .020 5.6 0   0  
bitvector/soft_float_2_true-unreach-call_true-no-overflow_true-termination.c.cil.c 0 900   920   160 9900 .85 0      - - - - 0 .76 .46 41 0   0   0 .019 .020 5.6 0   0  
bitvector/soft_float_3_true-unreach-call_true-no-overflow_true-termination.c.cil.c 0 860   880   160 13000 .72 .0041 - - - - 0 .69 .41 41 0   0   0 .019 .020 5.6 0   0  
bitvector/soft_float_4_true-unreach-call_true-no-overflow_true-termination.c.cil.c 0 860   880   170 11000 .55 .0041 - - - - 0 .75 .45 41 0   0   0 .019 .020 5.6 0   0  
bitvector/soft_float_5_true-unreach-call_true-no-overflow_true-termination.c.cil.c 0 900   920   170 12000 .86 .0041 - - - - 0 .64 .40 41 0   0   0 .021 .021 5.8 0   0  
bitvector-regression/implicitfloatconversion_false-unreach-call_true-termination.c 1 3.4 2.2 150 37 .57 .0082 1 3.7  2.0  250 0   .037  1 11     7.0   290   .75 0      1 3.4  2.0  250 0   .0041 1 .56   .57   20    .041 0     - -
bitvector-regression/implicitunsignedconversion_false-unreach-call_true-termination.c 1 3.2 1.9 150 36 .57 0      1 3.5  2.0  250 0   0      1 7.4   4.2   300   .66 0      1 3.4  2.0  240 0   0      1 .59   .59   20    .041 0     - -
bitvector-regression/integerpromotion_false-unreach-call_true-termination.c 1 3.5 2.1 150 39 .57 0      1 3.7  2.1  250 0   0      1 12     7.5   300   .75 0      1 3.3  1.9  250 0   0      1 .56   .56   20    .041 0     - -
bitvector-regression/recHanoi03_false-unreach-call_true-termination.c 1 8.7 7.5 150 93 .77 0      1 76    62    1500 0   0      -32 13     7.3   310   .71 0      1 3.6  2.1  250 0   0      1 .57   .57   20    .049 0     - -
bitvector-regression/signextension2_false-unreach-call_true-termination.c 1 3.3 2.2 160 40 .57 0      1 4.0  2.2  250 0   0      1 6.4   4.1   300   .66 0      1 3.5  2.0  250 0   0      1 .58   .57   20    .045 0     - -
bitvector-regression/signextension_false-unreach-call_true-termination.c 1 3.5 2.2 150 36 .57 0      1 3.5  1.9  240 0   0      1 6.6   3.8   300   .62 0      1 3.3  2.0  250 0   0      1 .61   .60   20    .045 0     - -
bitvector-regression/implicitunsignedconversion_true-unreach-call_true-termination.c 0 900   920   150 13000 .83 0      - - - - 0 .65 .39 41 0   0   0 .019 .020 5.6 0   0  
bitvector-regression/integerpromotion_true-unreach-call_true-termination.c 0 900   920   150 11000 .81 0      - - - - 0 .73 .46 40 0   0   0 .019 .020 5.6 0   0  
bitvector-regression/signextension2_true-unreach-call_true-termination.c 0 900   920   150 12000 .65 0      - - - - 0 .75 .46 40 0   0   0 .020 .021 5.7 0   0  
bitvector-regression/signextension_true-unreach-call_true-termination.c 0 900   920   150 13000 .76 0      - - - - 0 .76 .46 41 0   0   0 .020 .020 5.6 0   0  
bitvector-loops/diamond_false-unreach-call2.i 1 3.5 2.2 150 34 .59 0      1 4.1  2.3  250 0   0      -32 7.2   4.5   310   .62 0      1 3.7  2.1  250 0   0      1 .58   .58   20    .049 0     - -
bitvector-loops/overflow_false-unreach-call1.i 0 53   52   150 740 .37 0      0 .59 .36 41 0   0      0 .021 .021 5.6 0    0      0 .93 .60 47 0   0      0 .0022 .0027 .52 0     0     - -
bitvector-loops/verisec_sendmail__tTflag_arr_one_loop_false-unreach-call_true-termination.i 1 4.9 3.6 150 56 .69 0      0 92    88    810 0   0      -32 11     6.8   410   .66 .0041 1 3.7  2.1  250 0   0      1 .58   .58   20    .049 0     - -
sv-benchmarks/c/ status score witness inspect witness cpu (s) wall (s) mem (MB) energy (J) blkio-w (MB) blkio-r (MB) status score witness inspect witness cpu (s) wall (s) mem (MB) energy blkio-w (MB) blkio-r (MB) status score witness inspect witness cpu (s) wall (s) mem (MB) energy blkio-w (MB) blkio-r (MB) status score witness inspect witness cpu (s) wall (s) mem (MB) energy blkio-w (MB) blkio-r (MB) status score witness inspect witness cpu (s) wall (s) mem (MB) energy blkio-w (MB) blkio-r (MB) status score witness inspect witness cpu (s) wall (s) mem (MB) energy blkio-w (MB) blkio-r (MB) status score witness inspect witness cpu (s) wall (s) mem (MB) energy blkio-w (MB) blkio-r (MB)
total 50 13 28000 29000 8600 360000 41   140      14 11 310 260 6500 0   .34  14 -219 120 79 4100 8.6 .049 14 12 52 30 3300 0   .086 14 13 7.7 7.7 260 .81 .041 36 0 25 16 1500 0   0   36 0 .72 .75 200 0   0  
    correct results 13 13 370 360 2100 4400 9.4 .0082 11 11 130 91 4200 0   .041 5 5 44 27 1500 3.4 0     12 12 46 26 3000 0   .045 13 13 7.7 7.7 260 .81 .041 0 0
        correct true 0 0 0 0 0 0 0
        correct false 13 13 370 360 2100 4400 9.4 .0082 11 11 130 91 4200 0   .041 5 5 44 27 1500 3.4 0     12 12 46 26 3000 0   .045 13 13 7.7 7.7 260 .81 .041 0 0
    incorrect results 0 0 7 -224 63 37 2300 4.5 .049 0 0 0 0
        incorrect true 0 0 7 -224 63 37 2300 4.5 .049 0 0 0 0
        incorrect false 0 0 0 0 0 0 0
score (50 tasks, max score: 86) 13 11 -219 12 13 0 0
Run set verifuzz.sv-comp19_prop-reachsafety.ReachSafety-BitVectors cpa-seq-validate-violation-witnesses-verifuzz.sv-comp19_prop-reachsafety.ReachSafety-BitVectors uautomizer-validate-violation-witnesses-verifuzz.sv-comp19_prop-reachsafety.ReachSafety-BitVectors cpa-witness2test-validate-violation-witnesses-verifuzz.sv-comp19_prop-reachsafety.ReachSafety-BitVectors fshell-witness2test-validate-violation-witnesses-verifuzz.sv-comp19_prop-reachsafety.ReachSafety-BitVectors cpa-seq-validate-correctness-witnesses-verifuzz.sv-comp19_prop-reachsafety.ReachSafety-BitVectors uautomizer-validate-correctness-witnesses-verifuzz.sv-comp19_prop-reachsafety.ReachSafety-BitVectors