Tool VeriAbs 1.3.10 CPAchecker 1.7-svn 29852 ULTIMATE Automizer 0.1.23-635dfa2a CPA-witness2test 1.7-svn 29852 CProver witness2test 0.1 CPAchecker 1.7-svn 29852 ULTIMATE Automizer 0.1.23-635dfa2a
Limits timelimit: 900 s, memlimit: 15000 MB, CPU core limit: 8 timelimit: 90 s, memlimit: 7000 MB, CPU core limit: 2 timelimit: 900 s, memlimit: 7000 MB, CPU core limit: 2
Host apollon*
OS Linux 4.15.0-42-generic
System CPU: Intel Xeon E3-1230 v5 @ 3.40 GHz, cores: 8, frequency: 3.8 GHz, Turbo Boost: disabled; RAM: 33546 MB
Date of execution 2018-12-10 16:50:17 CET 2018-12-10 20:34:10 CET 2018-12-10 21:22:10 CET 2018-12-10 21:27:56 CET 2018-12-12 21:52:30 CET 2018-12-10 19:33:41 CET 2018-12-10 20:40:20 CET
Run set veriabs.sv-comp19_prop-reachsafety.ReachSafety-BitVectors cpa-seq-validate-violation-witnesses-veriabs.sv-comp19_prop-reachsafety.ReachSafety-BitVectors uautomizer-validate-violation-witnesses-veriabs.sv-comp19_prop-reachsafety.ReachSafety-BitVectors cpa-witness2test-validate-violation-witnesses-veriabs.sv-comp19_prop-reachsafety.ReachSafety-BitVectors fshell-witness2test-validate-violation-witnesses-veriabs.sv-comp19_prop-reachsafety.ReachSafety-BitVectors cpa-seq-validate-correctness-witnesses-veriabs.sv-comp19_prop-reachsafety.ReachSafety-BitVectors uautomizer-validate-correctness-witnesses-veriabs.sv-comp19_prop-reachsafety.ReachSafety-BitVectors
Options -witnessValidation -setprop witness.checkProgramHash=false -heap 5000m -benchmark -setprop cpa.predicate.memoryAllocationsAlwaysSucceed=true -setprop cpa.smg.memoryAllocationFunctions=malloc,__kmalloc,kmalloc,kzalloc,kzalloc_node,ldv_zalloc,ldv_malloc -setprop cpa.smg.arrayAllocationFunctions=calloc,kmalloc_array,kcalloc -setprop cpa.smg.zeroingMemoryAllocation=calloc,kzalloc,kcalloc,kzalloc_node,ldv_zalloc -setprop cpa.smg.deallocationFunctions=free,kfree,kfree_const -witness ../../results-verified/veriabs.2018-12-10_1650.logfiles/${rundefinition_name}.${inputfile_name}.files/witness.graphml --full-output --validate ../../results-verified/veriabs.2018-12-10_1650.logfiles/${rundefinition_name}.${inputfile_name}.files/witness.graphml -setprop witness.checkProgramHash=false -heap 5000m -benchmark -setprop analysis.summaryEdges=true -setprop cpa.callstack.skipVoidRecursion=true -setprop cpa.callstack.skipFunctionPointerRecursion=true -witness ../../results-verified/veriabs.2018-12-10_1650.logfiles/${rundefinition_name}.${inputfile_name}.files/witness.graphml --graphml-witness ../../results-verified/veriabs.2018-12-10_1650.logfiles/${rundefinition_name}.${inputfile_name}.files/witness.graphml -witnessValidation -setprop witness.checkProgramHash=false -heap 5000m -benchmark -setprop cpa.predicate.memoryAllocationsAlwaysSucceed=true -witness ../../results-verified/veriabs.2018-12-10_1650.logfiles/${rundefinition_name}.${inputfile_name}.files/witness.graphml --full-output --validate ../../results-verified/veriabs.2018-12-10_1650.logfiles/${rundefinition_name}.${inputfile_name}.files/witness.graphml
sv-benchmarks/c/ status score witness inspect witness cpu (s) wall (s) mem (MB) energy (J) blkio-w (MB) blkio-r (MB) status score witness inspect witness cpu (s) wall (s) mem (MB) energy blkio-w (MB) blkio-r (MB) status score witness inspect witness cpu (s) wall (s) mem (MB) energy blkio-w (MB) blkio-r (MB) status score witness inspect witness cpu (s) wall (s) mem (MB) energy blkio-w (MB) blkio-r (MB) status score witness inspect witness cpu (s) wall (s) mem (MB) energy blkio-w (MB) blkio-r (MB) status score witness inspect witness cpu (s) wall (s) mem (MB) energy blkio-w (MB) blkio-r (MB) status score witness inspect witness cpu (s) wall (s) mem (MB) energy blkio-w (MB) blkio-r (MB)
bitvector/byte_add_false-unreach-call_true-no-overflow_true-termination.i false(unreach-call) 1 wit inspect 28   15   310 250 .37 .016  false(unreach-call) 1 wit inspect 6.2  3.4  270 0   0   false(unreach-call) 1 --- inspect 40     23     610   .75 0    false(unreach-call) 1 --- inspect 5.2 2.9  250 0   0      false(unreach-call) 1 --- inspect .69   .69   21    .094 0   - --- inspect - --- inspect
bitvector/sum02_false-unreach-call_true-no-overflow.i unknown 0 --- inspect 530   510   1400 5200 11    .27   error (invalid witness file) 0 --- inspect .59 .36 41 0   0   error (2) 0 --- inspect .020 .022 5.6 0    0    error (invalid witness file) 0 --- inspect 1.2 .78 49 0   0      error (invalid witness file) 0 --- inspect .0021 .0027 .52 0     0   - --- inspect - --- inspect
bitvector/byte_add_1_true-unreach-call_true-no-overflow_true-termination.i true 2 wit inspect 79   41   760 780 150    0      - --- inspect - --- inspect - --- inspect - --- inspect true 2 wit inspect 17    9.4  460 0   0      timeout 0 --- inspect 960     930     3400   .68 .0041
bitvector/byte_add_2_true-unreach-call_true-no-overflow_true-termination.i true 2 wit inspect 77   40   850 720 140    0      - --- inspect - --- inspect - --- inspect - --- inspect true 2 wit inspect 18    9.9  470 0   0      timeout 0 --- inspect 960     930     3100   .72 0     
bitvector/gcd_1_true-unreach-call_true-no-overflow.i true 2 wit inspect 55   40   520 690 140    58      - --- inspect - --- inspect - --- inspect - --- inspect true 2 wit inspect 13    10    320 0   .0041 timeout 0 --- inspect 960     940     4700   .66 0     
bitvector/gcd_2_true-unreach-call_true-no-overflow.i true 2 wit inspect 81   67   520 910 150    0      - --- inspect - --- inspect - --- inspect - --- inspect true 2 wit inspect 170    160    560 0   0      timeout 0 --- inspect 960     950     680   .67 0     
bitvector/gcd_3_true-unreach-call_true-no-overflow.i true 2 wit inspect 81   67   780 1000 140    6.3    - --- inspect - --- inspect - --- inspect - --- inspect true 2 wit inspect 130    120    570 0   0      timeout 0 --- inspect 960     950     1600   1.6  0     
bitvector/gcd_4_true-unreach-call_true-no-overflow_true-termination.i true 2 wit inspect 57   38   700 600 150    0      - --- inspect - --- inspect - --- inspect - --- inspect true 2 wit inspect 12    8.5  350 0   0      true 2 --- inspect 15     8.8   460   .66 0     
bitvector/interleave_bits_true-unreach-call_true-no-overflow.i true 2 wit inspect 64   39   680 640 150    0      - --- inspect - --- inspect - --- inspect - --- inspect true 2 wit inspect 12    8.7  580 0   0      error (7) 0 --- inspect 350     330     2300   .68 0     
bitvector/jain_1_true-unreach-call_true-no-overflow_false-termination.i unknown 0 --- inspect 69   57   1100 660 14    0      - --- inspect - --- inspect - --- inspect - --- inspect error (invalid witness file) 0 --- inspect .60 .38 40 0   0      error (2) 0 --- inspect .020 .020 5.6 0    0     
bitvector/jain_2_true-unreach-call_true-no-overflow_false-termination.i unknown 0 --- inspect 84   73   2100 870 14    0      - --- inspect - --- inspect - --- inspect - --- inspect error (invalid witness file) 0 --- inspect .72 .45 41 0   0      error (2) 0 --- inspect .020 .021 5.7 0    0     
bitvector/jain_4_true-unreach-call_true-no-overflow_false-termination.i unknown 0 --- inspect 100   92   3000 1100 14    0      - --- inspect - --- inspect - --- inspect - --- inspect error (invalid witness file) 0 --- inspect .59 .36 41 0   0      error (2) 0 --- inspect .021 .021 5.6 0    0     
bitvector/jain_5_true-unreach-call_true-no-overflow.i true 1 wit inspect 5.8 2.3 200 46 .10 .0041 - --- inspect - --- inspect - --- inspect - --- inspect out of memory 0 --- inspect 800    790    7000 0   0      timeout 0 --- inspect 960     940     710   .63 0     
bitvector/jain_6_true-unreach-call_true-no-overflow_false-termination.i unknown 0 --- inspect 110   93   3000 1100 14    0      - --- inspect - --- inspect - --- inspect - --- inspect error (invalid witness file) 0 --- inspect .63 .39 41 0   0      error (2) 0 --- inspect .021 .022 5.6 0    0     
bitvector/jain_7_true-unreach-call_true-no-overflow_false-termination.i unknown 0 --- inspect 88   77   1900 1100 14    0      - --- inspect - --- inspect - --- inspect - --- inspect error (invalid witness file) 0 --- inspect .61 .39 42 0   0      error (2) 0 --- inspect .026 .026 5.6 0    0     
bitvector/modulus_true-unreach-call_true-no-overflow.i true 2 wit inspect 60   42   720 790 140    0      - --- inspect - --- inspect - --- inspect - --- inspect true 2 wit inspect 16    14    350 0   0      true 2 --- inspect 16     9.8   310   .75 0     
bitvector/num_conversion_1_true-unreach-call_true-no-overflow.i true 2 wit inspect 54   38   540 590 150    0      - --- inspect - --- inspect - --- inspect - --- inspect true 2 wit inspect 5.9  3.3  290 0   0      true 2 --- inspect 47     33     670   .75 0     
bitvector/num_conversion_2_true-unreach-call_true-no-overflow.i true 2 wit inspect 53   38   560 570 140    0      - --- inspect - --- inspect - --- inspect - --- inspect true 2 wit inspect 5.9  3.2  290 0   0      timeout 0 --- inspect 960     920     2200   .77 0     
bitvector/parity_true-unreach-call_true-no-overflow.i true 2 wit inspect 69   47   560 790 150    0      - --- inspect - --- inspect - --- inspect - --- inspect true 2 wit inspect 31    23    480 0   .0041 timeout 0 --- inspect 960     950     1100   .74 .0082
bitvector/sum02_true-unreach-call_true-no-overflow.i unknown 0 --- inspect 380   370   650 3800 7.3  0      - --- inspect - --- inspect - --- inspect - --- inspect error (invalid witness file) 0 --- inspect .76 .45 40 0   0      error (2) 0 --- inspect .022 .022 5.6 0    0     
bitvector/s3_clnt_1_false-unreach-call_true-no-overflow.BV.c.cil.c false(unreach-call) 1 wit inspect 43   25   400 480 .43 .0041 false(unreach-call) 1 wit inspect 7.5  4.0  280 0   0   false(unreach-call) 1 --- inspect 22     12     500   .68 0    false(unreach-call) 1 --- inspect 5.1 2.8  280 0   0      false(unreach-call) 1 --- inspect .75   .75   23    .16  0   - --- inspect - --- inspect
bitvector/s3_clnt_2_false-unreach-call_true-no-overflow.BV.c.cil.c false(unreach-call) 1 wit inspect 110   88   1000 1200 .44 .0041 false(unreach-call) 1 wit inspect 8.4  4.4  290 0   0   false(unreach-call) 1 --- inspect 23     13     500   .75 0    false(unreach-call) 1 --- inspect 5.6 3.1  280 0   0      false(unreach-call) 1 --- inspect .74   .74   23    .15  0   - --- inspect - --- inspect
bitvector/s3_clnt_3_false-unreach-call_true-no-overflow.BV.c.cil.c false(unreach-call) 1 wit inspect 97   80   920 1100 .43 .0041 false(unreach-call) 1 wit inspect 6.1  3.2  290 0   0   false(unreach-call) 1 --- inspect 22     13     420   .75 0    unknown 0 --- inspect 5.2 2.9  280 0   0      true -32 --- inspect .74   .76   22    .15  0   - --- inspect - --- inspect
bitvector/s3_clnt_1_true-unreach-call_true-no-overflow.BV.c.cil.c true 2 wit inspect 97   55   1100 1000 150    0      - --- inspect - --- inspect - --- inspect - --- inspect true 2 wit inspect 73    63    1000 0   0      true 2 --- inspect 51     29     820   .75 0     
bitvector/s3_clnt_2_true-unreach-call_true-no-overflow.BV.c.cil.c true 2 wit inspect 160   110   1300 1700 150    0      - --- inspect - --- inspect - --- inspect - --- inspect true 2 wit inspect 22    13    610 0   .041  true 2 --- inspect 52     29     950   .71 0     
bitvector/s3_clnt_3_true-unreach-call_true-no-overflow.BV.c.cil.c true 2 wit inspect 130   100   1000 1500 190    .012  - --- inspect - --- inspect - --- inspect - --- inspect true 2 wit inspect 16    9.1  580 0   0      out of memory 0 --- inspect 130     83     7000   .71 0     
bitvector/s3_srvr_1_alt_true-unreach-call_true-no-overflow.BV.c.cil.c unknown 0 --- inspect 570   550   690 7600 .68 0      - --- inspect - --- inspect - --- inspect - --- inspect error (invalid witness file) 0 --- inspect .78 .48 41 0   0      error (2) 0 --- inspect .022 .023 5.6 0    0     
bitvector/s3_srvr_1_true-unreach-call_true-no-overflow.BV.c.cil.c timeout 0 --- inspect 900   880   1200 8500 .66 0      - --- inspect - --- inspect - --- inspect - --- inspect error (invalid witness file) 0 --- inspect .61 .37 41 0   0      error (2) 0 --- inspect .022 .023 5.6 0    0     
bitvector/s3_srvr_2_alt_true-unreach-call_true-no-overflow_false-termination.BV.c.cil.c timeout 0 --- inspect 900   880   680 8600 .59 0      - --- inspect - --- inspect - --- inspect - --- inspect error (invalid witness file) 0 --- inspect .62 .39 40 0   0      error (2) 0 --- inspect .022 .023 5.6 0    0     
bitvector/s3_srvr_2_true-unreach-call_true-no-overflow_false-termination.BV.c.cil.c timeout 0 --- inspect 900   880   680 8000 .60 0      - --- inspect - --- inspect - --- inspect - --- inspect error (invalid witness file) 0 --- inspect .78 .49 40 0   0      error (2) 0 --- inspect .026 .027 5.6 0    0     
bitvector/s3_srvr_3_alt_true-unreach-call_true-no-overflow.BV.c.cil.c timeout 0 --- inspect 900   880   1200 7700 .47 0      - --- inspect - --- inspect - --- inspect - --- inspect error (invalid witness file) 0 --- inspect .60 .37 41 0   0      error (2) 0 --- inspect .020 .020 5.6 0    0     
bitvector/s3_srvr_3_true-unreach-call_true-no-overflow.BV.c.cil.c timeout 0 --- inspect 900   880   1300 7400 .56 0      - --- inspect - --- inspect - --- inspect - --- inspect error (invalid witness file) 0 --- inspect .69 .43 41 0   0      error (2) 0 --- inspect .021 .022 5.7 0    0     
bitvector/soft_float_1_true-unreach-call_true-no-overflow_true-termination.c.cil.c true 2 wit inspect 210   140   860 2200 150    6.1    - --- inspect - --- inspect - --- inspect - --- inspect true 2 wit inspect 25    17    890 0   0      false(unreach-call) -16 --- inspect 23     17     440   .66 0     
bitvector/soft_float_2_true-unreach-call_true-no-overflow_true-termination.c.cil.c true 2 wit inspect 100   70   990 1100 150    .0041 - --- inspect - --- inspect - --- inspect - --- inspect out of memory 0 --- inspect 840    760    7000 0   0      true 2 --- inspect 35     23     550   .66 0     
bitvector/soft_float_3_true-unreach-call_true-no-overflow_true-termination.c.cil.c true 1 wit inspect 180   120   940 2000 150    6.4    - --- inspect - --- inspect - --- inspect - --- inspect timeout 0 wit inspect 900    870    3800 0   0      false(unreach-call) -16 --- inspect 720     700     850   .62 0     
bitvector/soft_float_4_true-unreach-call_true-no-overflow_true-termination.c.cil.c true 2 wit inspect 220   150   850 2400 150    .020  - --- inspect - --- inspect - --- inspect - --- inspect true 2 wit inspect 160    160    530 0   0      true 2 --- inspect 370     340     770   .71 0     
bitvector/soft_float_5_true-unreach-call_true-no-overflow_true-termination.c.cil.c true 2 wit inspect 98   70   800 1200 150    40      - --- inspect - --- inspect - --- inspect - --- inspect out of memory 0 --- inspect 870    800    7000 0   0      true 2 --- inspect 25     15     600   .62 0     
bitvector-regression/implicitfloatconversion_false-unreach-call_true-termination.c false(unreach-call) 1 wit inspect 8.4 3.2 300 69 .11 .25   false(unreach-call) 1 wit inspect 4.4  2.5  250 0   0   false(unreach-call) 1 --- inspect 13     8.0   300   .75 0    false(unreach-call) 1 --- inspect 4.1 2.4  240 0   .0041 false(unreach-call) 1 --- inspect .59   .59   20    .041 0   - --- inspect - --- inspect
bitvector-regression/implicitunsignedconversion_false-unreach-call_true-termination.c false(unreach-call) 1 wit inspect 8.6 3.4 270 66 .11 .0041 false(unreach-call) 1 wit inspect 3.7  2.1  250 0   0   false(unreach-call) 1 --- inspect 8.7   5.1   300   .66 0    false(unreach-call) 1 --- inspect 3.4 2.0  240 0   0      false(unreach-call) 1 --- inspect .56   .56   20    .041 0   - --- inspect - --- inspect
bitvector-regression/integerpromotion_false-unreach-call_true-termination.c false(unreach-call) 1 wit inspect 6.9 3.0 270 61 .11 0      false(unreach-call) 1 wit inspect 3.7  2.0  250 0   0   false(unreach-call) 1 --- inspect 12     7.0   300   .75 .14 false(unreach-call) 1 --- inspect 3.6 2.1  240 0   0      false(unreach-call) 1 --- inspect .56   .56   20    .041 0   - --- inspect - --- inspect
bitvector-regression/recHanoi03_false-unreach-call_true-termination.c error 0 --- inspect 9.7 3.5 200 69 .32 0      error (invalid witness file) 0 --- inspect .57 .35 40 0   0   error (2) 0 --- inspect .020 .023 5.6 0    0    error (invalid witness file) 0 --- inspect 1.2 .78 47 0   0      error (invalid witness file) 0 --- inspect .0036 .0048 .53 0     0   - --- inspect - --- inspect
bitvector-regression/signextension2_false-unreach-call_true-termination.c false(unreach-call) 1 wit inspect 8.7 3.4 260 81 .11 0      false(unreach-call) 1 wit inspect 3.6  2.0  250 0   0   true -32 --- inspect 6.7   4.0   290   .66 0    false(unreach-call) 1 --- inspect 3.5 2.0  250 0   0      false(unreach-call) 1 --- inspect .56   .56   20    .045 0   - --- inspect - --- inspect
bitvector-regression/signextension_false-unreach-call_true-termination.c false(unreach-call) 1 wit inspect 8.9 3.4 300 83 .11 0      false(unreach-call) 1 wit inspect 4.7  2.6  250 0   0   true -32 --- inspect 6.4   4.0   300   .66 0    false(unreach-call) 1 --- inspect 4.2 2.4  250 0   0      false(unreach-call) 1 --- inspect .57   .58   20    .045 0   - --- inspect - --- inspect
bitvector-regression/implicitunsignedconversion_true-unreach-call_true-termination.c true 2 wit inspect 12   6.4 440 110 150    0      - --- inspect - --- inspect - --- inspect - --- inspect true 2 wit inspect 3.5  2.0  250 0   0      true 2 --- inspect 7.0   4.0   310   .66 0     
bitvector-regression/integerpromotion_true-unreach-call_true-termination.c true 2 wit inspect 15   7.5 420 130 140    0      - --- inspect - --- inspect - --- inspect - --- inspect true 2 wit inspect 3.8  2.2  250 0   0      true 2 --- inspect 12     7.0   300   .75 .0041
bitvector-regression/signextension2_true-unreach-call_true-termination.c true 2 wit inspect 13   6.5 450 110 190    0      - --- inspect - --- inspect - --- inspect - --- inspect true 2 wit inspect 4.2  2.4  250 0   0      true 2 --- inspect 8.6   4.8   310   .66 0     
bitvector-regression/signextension_true-unreach-call_true-termination.c true 2 wit inspect 12   6.5 450 100 190    0      - --- inspect - --- inspect - --- inspect - --- inspect true 2 wit inspect 3.7  2.1  250 0   0      true 2 --- inspect 7.6   4.7   310   .66 0     
bitvector-loops/diamond_false-unreach-call2.i false(unreach-call) 1 wit inspect 18   9.1 280 160 .34 0      false(unreach-call) 1 wit inspect 5.2  2.8  260 0   0   false(unreach-call) 1 --- inspect 7.3   4.6   310   .66 0    false(unreach-call) 1 --- inspect 3.9 2.2  250 0   0      false(unreach-call) 1 --- inspect .58   .58   20    .049 0   - --- inspect - --- inspect
bitvector-loops/overflow_false-unreach-call1.i false(unreach-call) 1 wit inspect 220   200   1800 3100 .11 1.2    timeout 0 wit inspect 98    86    1800 0   0   true -32 --- inspect 8.4   4.7   310   .66 0    false(unreach-call) 1 --- inspect 7.0 5.5  250 0   0      false(unreach-call) 1 --- inspect 4.3    4.3    20    .045 0   - --- inspect - --- inspect
bitvector-loops/verisec_sendmail__tTflag_arr_one_loop_false-unreach-call_true-termination.i false(unreach-call) 0 wit inspect 220   210   770 2800 .42 0      true -32 wit inspect 4.9  2.7  260 0   0   timeout 0 --- inspect 97     86     630   .67 0    unknown 0 --- inspect 4.5 2.5  250 0   0      error (2) 0 --- inspect .61   .60   21    .037 0   - --- inspect - --- inspect
sv-benchmarks/c/ status score witness inspect witness cpu (s) wall (s) mem (MB) energy (J) blkio-w (MB) blkio-r (MB) status score witness inspect witness cpu (s) wall (s) mem (MB) energy blkio-w (MB) blkio-r (MB) status score witness inspect witness cpu (s) wall (s) mem (MB) energy blkio-w (MB) blkio-r (MB) status score witness inspect witness cpu (s) wall (s) mem (MB) energy blkio-w (MB) blkio-r (MB) status score witness inspect witness cpu (s) wall (s) mem (MB) energy blkio-w (MB) blkio-r (MB) status score witness inspect witness cpu (s) wall (s) mem (MB) energy blkio-w (MB) blkio-r (MB) status score witness inspect witness cpu (s) wall (s) mem (MB) energy blkio-w (MB) blkio-r (MB)
total 50 57 9200 8200 43000 93000 3600    120   14 -22 160   120   4800 0   0   14 -88 270 180 4800 8.4 .14 14 10 58 34 3200 0   .0041 14 -22 11    11    250 .90 0   36 40 4200 3900 35000 0   .049 36 -8 9600 9100 35000 17   .016 
    correct results 33 55 2400 1700 22000 26000 3400    110   10 10 53   29   2600 0   0   8 8 150 85 3200 5.7 .14 10 10 46 27 2500 0   .0041 10 10 9.9  9.9  210 .71 0   20 40 740 650 9400 0   .049 12 24 650 510 6300 8.3 .0041
        correct true 22 44 1800 1200 16000 20000 3400    110   0 0 0 0 20 40 740 650 9400 0   .049 12 24 650 510 6300 8.3 .0041
        correct false 11 11 550 440 6100 6600 2.7  1.4 10 10 53   29   2600 0   0   8 8 150 85 3200 5.7 .14 10 10 46 27 2500 0   .0041 10 10 9.9  9.9  210 .71 0   0 0
    correct-unconfimed results 3 2 410 330 1900 4800 150    6.5 0 0 0 0 0 0
        correct-unconfirmed true 2 2 190 120 1100 2000 150    6.5 0 0 0 0 0 0
        correct-unconfirmed false 1 0 220 210 770 2800 .42 0   0 0 0 0 0 0
    incorrect results 0 1 -32 4.9 2.7 260 0   0   3 -96 22 13 900 2.0 0    0 1 -32 .74 .76 22 .15 0   0 2 -32 750 710 1300 1.3 0     
        incorrect true 0 1 -32 4.9 2.7 260 0   0   3 -96 22 13 900 2.0 0    0 1 -32 .74 .76 22 .15 0   0 0
        incorrect false 0 0 0 0 0 0 2 -32 750 710 1300 1.3 0     
score (50 tasks, max score: 86) 57 -22 -88 10 -22 40 -8
Run set veriabs.sv-comp19_prop-reachsafety.ReachSafety-BitVectors cpa-seq-validate-violation-witnesses-veriabs.sv-comp19_prop-reachsafety.ReachSafety-BitVectors uautomizer-validate-violation-witnesses-veriabs.sv-comp19_prop-reachsafety.ReachSafety-BitVectors cpa-witness2test-validate-violation-witnesses-veriabs.sv-comp19_prop-reachsafety.ReachSafety-BitVectors fshell-witness2test-validate-violation-witnesses-veriabs.sv-comp19_prop-reachsafety.ReachSafety-BitVectors cpa-seq-validate-correctness-witnesses-veriabs.sv-comp19_prop-reachsafety.ReachSafety-BitVectors uautomizer-validate-correctness-witnesses-veriabs.sv-comp19_prop-reachsafety.ReachSafety-BitVectors