Tool symbiotic 6.0.3-77d4af47 CPAchecker 1.7-svn 29852 ULTIMATE Automizer 0.1.23-635dfa2a CPA-witness2test 1.7-svn 29852 CProver witness2test 0.1 CPAchecker 1.7-svn 29852 ULTIMATE Automizer 0.1.23-635dfa2a
Limits timelimit: 900 s, memlimit: 15000 MB, CPU core limit: 8 timelimit: 90 s, memlimit: 7000 MB, CPU core limit: 2 timelimit: 900 s, memlimit: 7000 MB, CPU core limit: 2
Host apollon* [apollon013; apollon098] apollon*
OS Linux 4.15.0-42-generic
System CPU: Intel Xeon E3-1230 v5 @ 3.40 GHz, cores: 8, frequency: 3.8 GHz, Turbo Boost: disabled; RAM: 33546 MB
Date of execution 2018-12-07 21:42:05 CET 2018-12-08 23:40:56 CET 2018-12-09 00:46:04 CET 2018-12-09 01:29:54 CET 2018-12-12 21:10:03 CET 2018-12-08 22:46:12 CET 2018-12-08 23:47:25 CET
Run set symbiotic.sv-comp19_prop-reachsafety.ReachSafety-BitVectors cpa-seq-validate-violation-witnesses-symbiotic.sv-comp19_prop-reachsafety.ReachSafety-BitVectors uautomizer-validate-violation-witnesses-symbiotic.sv-comp19_prop-reachsafety.ReachSafety-BitVectors cpa-witness2test-validate-violation-witnesses-symbiotic.sv-comp19_prop-reachsafety.ReachSafety-BitVectors fshell-witness2test-validate-violation-witnesses-symbiotic.sv-comp19_prop-reachsafety.ReachSafety-BitVectors cpa-seq-validate-correctness-witnesses-symbiotic.sv-comp19_prop-reachsafety.ReachSafety-BitVectors uautomizer-validate-correctness-witnesses-symbiotic.sv-comp19_prop-reachsafety.ReachSafety-BitVectors
Options --witness witness.graphml -witnessValidation -setprop witness.checkProgramHash=false -heap 5000m -benchmark -setprop cpa.predicate.memoryAllocationsAlwaysSucceed=true -setprop cpa.smg.memoryAllocationFunctions=malloc,__kmalloc,kmalloc,kzalloc,kzalloc_node,ldv_zalloc,ldv_malloc -setprop cpa.smg.arrayAllocationFunctions=calloc,kmalloc_array,kcalloc -setprop cpa.smg.zeroingMemoryAllocation=calloc,kzalloc,kcalloc,kzalloc_node,ldv_zalloc -setprop cpa.smg.deallocationFunctions=free,kfree,kfree_const -witness ../../results-verified/symbiotic.2018-12-07_2142.logfiles/${rundefinition_name}.${inputfile_name}.files/witness.graphml --full-output --validate ../../results-verified/symbiotic.2018-12-07_2142.logfiles/${rundefinition_name}.${inputfile_name}.files/witness.graphml -setprop witness.checkProgramHash=false -heap 5000m -benchmark -setprop analysis.summaryEdges=true -setprop cpa.callstack.skipVoidRecursion=true -setprop cpa.callstack.skipFunctionPointerRecursion=true -witness ../../results-verified/symbiotic.2018-12-07_2142.logfiles/${rundefinition_name}.${inputfile_name}.files/witness.graphml --graphml-witness ../../results-verified/symbiotic.2018-12-07_2142.logfiles/${rundefinition_name}.${inputfile_name}.files/witness.graphml -witnessValidation -setprop witness.checkProgramHash=false -heap 5000m -benchmark -setprop cpa.predicate.memoryAllocationsAlwaysSucceed=true -witness ../../results-verified/symbiotic.2018-12-07_2142.logfiles/${rundefinition_name}.${inputfile_name}.files/witness.graphml --full-output --validate ../../results-verified/symbiotic.2018-12-07_2142.logfiles/${rundefinition_name}.${inputfile_name}.files/witness.graphml
sv-benchmarks/c/ status score witness inspect witness cpu (s) wall (s) mem (MB) energy (J) blkio-w (MB) blkio-r (MB) status score witness inspect witness cpu (s) wall (s) mem (MB) energy blkio-w (MB) blkio-r (MB) status score witness inspect witness cpu (s) wall (s) mem (MB) energy blkio-w (MB) blkio-r (MB) status score witness inspect witness cpu (s) wall (s) mem (MB) energy blkio-w (MB) blkio-r (MB) status score witness inspect witness cpu (s) wall (s) mem (MB) energy blkio-w (MB) blkio-r (MB) status score witness inspect witness cpu (s) wall (s) mem (MB) energy blkio-w (MB) blkio-r (MB) status score witness inspect witness cpu (s) wall (s) mem (MB) energy blkio-w (MB) blkio-r (MB)
bitvector/byte_add_false-unreach-call_true-no-overflow_true-termination.i 1 .35 .34 19 4.1 0     0      1 4.6  2.5  250 0   0      -32 7.7   4.8   300   .62 0   1 3.9  2.3  250 0   0      1 .59   .59   20    .057 0      - -
bitvector/sum02_false-unreach-call_true-no-overflow.i 0 900    900    370 11000   .025 0      0 .55 .34 40 0   0      0 .025 .027 5.6 0    0   0 .93 .60 47 0   0      0 .0065 .0083 .52 0     0      - -
bitvector/byte_add_1_true-unreach-call_true-no-overflow_true-termination.i 2 .37 .36 18 4.5 0     0      - - - - 2 12    6.2  370 0   0      0 960     920     1000   .78 0     
bitvector/byte_add_2_true-unreach-call_true-no-overflow_true-termination.i 2 .36 .35 18 4.3 0     0      - - - - 2 9.8  5.4  370 0   0      0 960     920     1000   1.5  0     
bitvector/gcd_1_true-unreach-call_true-no-overflow.i 2 .51 .50 21 7.2 0     .28   - - - - 2 11    8.6  320 0   0      0 960     950     540   .63 0     
bitvector/gcd_2_true-unreach-call_true-no-overflow.i 2 26    26    42 350   0     0      - - - - 2 170    160    560 0   0      0 960     950     640   1.5  0     
bitvector/gcd_3_true-unreach-call_true-no-overflow.i 2 33    33    42 530   0     0      - - - - 2 120    120    560 0   0      0 960     950     950   .65 0     
bitvector/gcd_4_true-unreach-call_true-no-overflow_true-termination.i 2 .16 .16 15 1.5 0     0      - - - - 2 7.2  4.7  320 0   .0041 2 42     32     590   .62 0     
bitvector/interleave_bits_true-unreach-call_true-no-overflow.i 2 .17 .17 18 2.1 0     0      - - - - 2 14    9.1  380 0   0      2 220     200     660   .71 0     
bitvector/jain_1_true-unreach-call_true-no-overflow_false-termination.i 0 900    900    340 8100   .025 0      - - - - 0 .70 .43 40 0   0      0 .027 .028 5.6 0    0     
bitvector/jain_2_true-unreach-call_true-no-overflow_false-termination.i 0 900    900    440 7300   .016 0      - - - - 0 .77 .46 41 0   0      0 .027 .027 5.6 0    0     
bitvector/jain_4_true-unreach-call_true-no-overflow_false-termination.i 0 170    180    15000 2400   .21  0      - - - - 0 .70 .43 40 0   0      0 .022 .023 5.6 0    0     
bitvector/jain_5_true-unreach-call_true-no-overflow.i 0 180    180    15000 2400   .16  0      - - - - 0 .59 .37 40 0   0      0 .026 .027 5.6 0    0     
bitvector/jain_6_true-unreach-call_true-no-overflow_false-termination.i 0 170    180    15000 2700   .17  0      - - - - 0 .60 .36 40 0   0      0 .026 .028 5.6 0    0     
bitvector/jain_7_true-unreach-call_true-no-overflow_false-termination.i 0 170    180    15000 3000   .094 .0041 - - - - 0 .74 .47 41 0   0      0 .024 .025 5.6 0    0     
bitvector/modulus_true-unreach-call_true-no-overflow.i 0 900    900    150 11000   .029 0      - - - - 0 .68 .42 40 0   0      0 .028 .028 5.5 0    0     
bitvector/num_conversion_1_true-unreach-call_true-no-overflow.i 2 .15 .15 15 1.7 0     0      - - - - 2 6.0  3.2  280 0   0      2 37     24     560   .71 0     
bitvector/num_conversion_2_true-unreach-call_true-no-overflow.i 2 .19 .19 17 2.2 0     .0041 - - - - 2 6.4  3.5  290 0   0      0 960     930     2200   .72 0     
bitvector/parity_true-unreach-call_true-no-overflow.i 2 26    26    25 360   0     0      - - - - 2 36    27    470 0   0      0 960     950     1100   .75 .074 
bitvector/sum02_true-unreach-call_true-no-overflow.i 0 900    900    380 10000   .025 0      - - - - 0 .71 .43 40 0   0      0 .022 .022 5.6 0    0     
bitvector/s3_clnt_1_false-unreach-call_true-no-overflow.BV.c.cil.c 1 1.3  1.3  20 18   0     0      1 15    8.5  430 0   .041  -32 8.4   5.2   310   .62 0   0 4.3  2.4  250 0   0      -32 .62   .62   20    .12  0      - -
bitvector/s3_clnt_2_false-unreach-call_true-no-overflow.BV.c.cil.c 1 1.8  1.8  20 23   0     0      1 29    21    480 0   0      -32 8.4   4.7   310   .66 0   0 5.6  3.2  260 0   0      -32 .65   .65   20    .11  0      - -
bitvector/s3_clnt_3_false-unreach-call_true-no-overflow.BV.c.cil.c 1 .52 .52 18 6.5 0     0      1 9.6  5.1  420 0   0      -32 8.4   4.8   310   .62 0   0 5.6  3.1  250 0   0      -32 .63   .63   20    .11  0      - -
bitvector/s3_clnt_1_true-unreach-call_true-no-overflow.BV.c.cil.c 2 .96 .96 18 12   0     0      - - - - 2 84    73    1000 0   0      2 45     27     780   .68 0     
bitvector/s3_clnt_2_true-unreach-call_true-no-overflow.BV.c.cil.c 2 .91 .91 18 14   0     0      - - - - 2 17    10    600 0   0      2 58     33     970   .71 0     
bitvector/s3_clnt_3_true-unreach-call_true-no-overflow.BV.c.cil.c 2 .92 .91 18 12   0     0      - - - - 2 15    8.3  550 0   0      2 31     18     820   .62 0     
bitvector/s3_srvr_1_alt_true-unreach-call_true-no-overflow.BV.c.cil.c 0 900    900    540 9900   .025 0      - - - - 0 .77 .47 41 0   0      0 .021 .022 5.7 0    0     
bitvector/s3_srvr_1_true-unreach-call_true-no-overflow.BV.c.cil.c 0 900    900    880 9400   .025 0      - - - - 0 .63 .40 41 0   0      0 .021 .022 5.6 0    0     
bitvector/s3_srvr_2_alt_true-unreach-call_true-no-overflow_false-termination.BV.c.cil.c 0 900    900    150 8600   .025 0      - - - - 0 .59 .36 41 0   0      0 .027 .028 5.6 0    0     
bitvector/s3_srvr_2_true-unreach-call_true-no-overflow_false-termination.BV.c.cil.c 0 900    900    160 9100   .020 0      - - - - 0 .78 .47 40 0   0      0 .025 .026 5.6 0    0     
bitvector/s3_srvr_3_alt_true-unreach-call_true-no-overflow.BV.c.cil.c 0 900    900    230 11000   .025 0      - - - - 0 .74 .45 40 0   0      0 .021 .022 5.6 0    0     
bitvector/s3_srvr_3_true-unreach-call_true-no-overflow.BV.c.cil.c 0 900    900    220 11000   .025 0      - - - - 0 .79 .49 42 0   0      0 .025 .025 5.6 0    0     
bitvector/soft_float_1_true-unreach-call_true-no-overflow_true-termination.c.cil.c 0 900    900    160 11000   .020 0      - - - - 0 .78 .47 42 0   0      0 .022 .022 5.6 0    0     
bitvector/soft_float_2_true-unreach-call_true-no-overflow_true-termination.c.cil.c 2 2.8  2.8  24 39   0     0      - - - - 0 760    690    7000 0   0      2 41     26     540   .66 0     
bitvector/soft_float_3_true-unreach-call_true-no-overflow_true-termination.c.cil.c 1 9.1  9.1  31 130   0     0      - - - - 0 800    740    7000 0   0      0 960     900     830   .79 .0041
bitvector/soft_float_4_true-unreach-call_true-no-overflow_true-termination.c.cil.c 0 900    900    41 11000   .025 0      - - - - 0 .58 .36 40 0   0      0 .021 .022 5.6 0    0     
bitvector/soft_float_5_true-unreach-call_true-no-overflow_true-termination.c.cil.c 2 2.8  2.8  24 34   0     0      - - - - 0 710    650    7000 0   0      2 27     16     590   .66 0     
bitvector-regression/implicitfloatconversion_false-unreach-call_true-termination.c 1 .18 .18 16 1.6 0     0      1 4.0  2.2  250 0   0      1 12     7.4   300   .68 0   1 3.8  2.2  250 0   0      1 .57   .57   20    .041 .0041 - -
bitvector-regression/implicitunsignedconversion_false-unreach-call_true-termination.c 1 .17 .17 16 2.7 0     0      1 4.0  2.3  250 0   .0041 1 6.7   3.8   300   .66 0   1 4.3  2.5  250 0   0      1 .56   .56   20    .041 0      - -
bitvector-regression/integerpromotion_false-unreach-call_true-termination.c 1 .16 .15 16 2.2 0     0      1 4.4  2.4  250 0   0      1 13     7.8   300   .71 0   1 3.5  2.0  250 0   0      1 .56   .56   20    .041 .0041 - -
bitvector-regression/recHanoi03_false-unreach-call_true-termination.c 0 900    900    660 11000   .025 0      0 .56 .34 40 0   0      0 .021 .021 5.6 0    0   0 .92 .60 49 0   0      0 .0020 .0025 .52 0     0      - -
bitvector-regression/signextension2_false-unreach-call_true-termination.c 1 .16 .15 16 1.7 0     0      1 4.4  2.5  250 0   0      1 6.8   4.4   300   .62 0   1 3.4  2.0  250 0   0      1 .56   .56   20    .045 0      - -
bitvector-regression/signextension_false-unreach-call_true-termination.c 1 .21 .20 16 1.7 0     0      1 3.9  2.2  250 0   0      1 6.8   3.9   310   .62 0   1 3.4  1.9  250 0   .0041 1 .56   .57   20    .045 0      - -
bitvector-regression/implicitunsignedconversion_true-unreach-call_true-termination.c 2 .14 .14 16 1.4 0     0      - - - - 2 3.7  2.1  250 0   0      2 8.0   4.8   310   .66 0     
bitvector-regression/integerpromotion_true-unreach-call_true-termination.c 2 .14 .14 15 1.4 0     0      - - - - 2 4.3  2.4  250 0   0      2 12     7.5   300   .75 .13  
bitvector-regression/signextension2_true-unreach-call_true-termination.c 2 .17 .16 16 1.6 0     0      - - - - 2 3.9  2.2  250 0   0      2 7.8   4.4   310   .66 0     
bitvector-regression/signextension_true-unreach-call_true-termination.c 2 .14 .13 17 1.5 0     0      - - - - 2 5.0  2.7  250 0   0      2 7.3   4.5   310   .62 0     
bitvector-loops/diamond_false-unreach-call2.i 1 .20 .20 17 2.6 0     0      1 4.6  2.6  250 0   0      -32 6.9   4.3   300   .62 0   1 4.0  2.3  250 0   0      1 .60   .60   20    .049 0      - -
bitvector-loops/overflow_false-unreach-call1.i 1 .16 .16 16 2.2 0     0      0 98    84    1800 0   0      -32 7.9   4.9   310   .62 0   1 6.8  5.4  240 0   0      1 4.1    4.1    20    .045 0      - -
bitvector-loops/verisec_sendmail__tTflag_arr_one_loop_false-unreach-call_true-termination.i 0 .52 .52 18 7.4 0     0      0 92    88    740 0   0      -32 7.0   4.1   310   .62 0   -32 3.9  2.2  250 0   0      -32 .57   .58   20    .049 0      - -
sv-benchmarks/c/ status score witness inspect witness cpu (s) wall (s) mem (MB) energy (J) blkio-w (MB) blkio-r (MB) status score witness inspect witness cpu (s) wall (s) mem (MB) energy blkio-w (MB) blkio-r (MB) status score witness inspect witness cpu (s) wall (s) mem (MB) energy blkio-w (MB) blkio-r (MB) status score witness inspect witness cpu (s) wall (s) mem (MB) energy blkio-w (MB) blkio-r (MB) status score witness inspect witness cpu (s) wall (s) mem (MB) energy blkio-w (MB) blkio-r (MB) status score witness inspect witness cpu (s) wall (s) mem (MB) energy blkio-w (MB) blkio-r (MB) status score witness inspect witness cpu (s) wall (s) mem (MB) energy blkio-w (MB) blkio-r (MB)
total 50 50 13000    13000    65000 150000   .97 .29 14 10 280 220 5700 0   .045 14 -219 100 60 3700 7.7 0   14 -24 54   33   3100 0   .0041 14 -120 11   11   240 .75 .0082 36 34 2800 2500 29000 0   .0041 36 24 8200 7900 15000 15   .21
    correct results 30 49 100    100    590 1400   0    .28 10 10 84 51 3100 0   .045 5 5 45 27 1500 3.3 0   8 8 33   21   2000 0   .0041 8 8 8.1 8.1 160 .36 .0082 17 34 520 450 7100 0   .0041 12 24 540 400 6700 8.1 .13
        correct true 19 38 97    97    400 1400   0    .28 0 0 0 0 17 34 520 450 7100 0   .0041 12 24 540 400 6700 8.1 .13
        correct false 11 11 5.2  5.2  190 66   0    0    10 10 84 51 3100 0   .045 5 5 45 27 1500 3.3 0   8 8 33   21   2000 0   .0041 8 8 8.1 8.1 160 .36 .0082 0 0
    correct-unconfimed results 2 1 9.6  9.6  49 140   0    0    0 0 0 0 0 0
        correct-unconfirmed true 1 1 9.1  9.1  31 130   0    0    0 0 0 0 0 0
        correct-unconfirmed false 1 0 .52 .52 18 7.4 0    0    0 0 0 0 0 0
    incorrect results 0 0 7 -224 55 33 2100 4.4 0   1 -32 3.9 2.2 250 0   0      4 -128 2.5 2.5 81 .39 0      0 0
        incorrect true 0 0 7 -224 55 33 2100 4.4 0   1 -32 3.9 2.2 250 0   0      4 -128 2.5 2.5 81 .39 0      0 0
        incorrect false 0 0 0 0 0 0 0
score (50 tasks, max score: 86) 50 10 -219 -24 -120 34 24
Run set symbiotic.sv-comp19_prop-reachsafety.ReachSafety-BitVectors cpa-seq-validate-violation-witnesses-symbiotic.sv-comp19_prop-reachsafety.ReachSafety-BitVectors uautomizer-validate-violation-witnesses-symbiotic.sv-comp19_prop-reachsafety.ReachSafety-BitVectors cpa-witness2test-validate-violation-witnesses-symbiotic.sv-comp19_prop-reachsafety.ReachSafety-BitVectors fshell-witness2test-validate-violation-witnesses-symbiotic.sv-comp19_prop-reachsafety.ReachSafety-BitVectors cpa-seq-validate-correctness-witnesses-symbiotic.sv-comp19_prop-reachsafety.ReachSafety-BitVectors uautomizer-validate-correctness-witnesses-symbiotic.sv-comp19_prop-reachsafety.ReachSafety-BitVectors