Tool PeSCo 1.7-svn b8d6131600+ CPAchecker 1.7-svn 29852 ULTIMATE Automizer 0.1.23-635dfa2a CPA-witness2test 1.7-svn 29852 CProver witness2test 0.1 CPAchecker 1.7-svn 29852 ULTIMATE Automizer 0.1.23-635dfa2a
Limits timelimit: 900 s, memlimit: 15000 MB, CPU core limit: 8 timelimit: 90 s, memlimit: 7000 MB, CPU core limit: 2 timelimit: 900 s, memlimit: 7000 MB, CPU core limit: 2
Host apollon* [apollon004; apollon069; apollon137; apollon154] [apollon004; apollon006; apollon021; apollon061; apollon109; apollon155] apollon*
OS Linux 4.15.0-42-generic
System CPU: Intel Xeon E3-1230 v5 @ 3.40 GHz, cores: 8, frequency: 3.8 GHz, Turbo Boost: disabled; RAM: 33546 MB
Date of execution 2018-12-06 12:44:04 CET 2018-12-08 07:39:30 CET 2018-12-08 12:16:42 CET 2018-12-08 13:32:07 CET 2018-12-12 20:37:42 CET 2018-12-08 05:07:50 CET 2018-12-08 09:11:31 CET
Run set pesco.sv-comp19_prop-reachsafety.ReachSafety-BitVectors cpa-seq-validate-violation-witnesses-pesco.sv-comp19_prop-reachsafety.ReachSafety-BitVectors uautomizer-validate-violation-witnesses-pesco.sv-comp19_prop-reachsafety.ReachSafety-BitVectors cpa-witness2test-validate-violation-witnesses-pesco.sv-comp19_prop-reachsafety.ReachSafety-BitVectors fshell-witness2test-validate-violation-witnesses-pesco.sv-comp19_prop-reachsafety.ReachSafety-BitVectors cpa-seq-validate-correctness-witnesses-pesco.sv-comp19_prop-reachsafety.ReachSafety-BitVectors uautomizer-validate-correctness-witnesses-pesco.sv-comp19_prop-reachsafety.ReachSafety-BitVectors
Options -svcomp19-pesco -heap 10000M -stack 2048k -benchmark -timelimit 900s -witnessValidation -setprop witness.checkProgramHash=false -heap 5000m -benchmark -setprop cpa.predicate.memoryAllocationsAlwaysSucceed=true -setprop cpa.smg.memoryAllocationFunctions=malloc,__kmalloc,kmalloc,kzalloc,kzalloc_node,ldv_zalloc,ldv_malloc -setprop cpa.smg.arrayAllocationFunctions=calloc,kmalloc_array,kcalloc -setprop cpa.smg.zeroingMemoryAllocation=calloc,kzalloc,kcalloc,kzalloc_node,ldv_zalloc -setprop cpa.smg.deallocationFunctions=free,kfree,kfree_const -witness ../../results-verified/pesco.2018-12-06_1244.logfiles/${rundefinition_name}.${inputfile_name}.files/witness.graphml --full-output --validate ../../results-verified/pesco.2018-12-06_1244.logfiles/${rundefinition_name}.${inputfile_name}.files/witness.graphml -setprop witness.checkProgramHash=false -heap 5000m -benchmark -setprop analysis.summaryEdges=true -setprop cpa.callstack.skipVoidRecursion=true -setprop cpa.callstack.skipFunctionPointerRecursion=true -witness ../../results-verified/pesco.2018-12-06_1244.logfiles/${rundefinition_name}.${inputfile_name}.files/witness.graphml --graphml-witness ../../results-verified/pesco.2018-12-06_1244.logfiles/${rundefinition_name}.${inputfile_name}.files/witness.graphml -witnessValidation -setprop witness.checkProgramHash=false -heap 5000m -benchmark -setprop cpa.predicate.memoryAllocationsAlwaysSucceed=true -witness ../../results-verified/pesco.2018-12-06_1244.logfiles/${rundefinition_name}.${inputfile_name}.files/witness.graphml --full-output --validate ../../results-verified/pesco.2018-12-06_1244.logfiles/${rundefinition_name}.${inputfile_name}.files/witness.graphml
sv-benchmarks/c/ status score witness inspect witness cpu (s) wall (s) mem (MB) energy (J) blkio-w (MB) blkio-r (MB) status score witness inspect witness cpu (s) wall (s) mem (MB) energy blkio-w (MB) blkio-r (MB) status score witness inspect witness cpu (s) wall (s) mem (MB) energy blkio-w (MB) blkio-r (MB) status score witness inspect witness cpu (s) wall (s) mem (MB) energy blkio-w (MB) blkio-r (MB) status score witness inspect witness cpu (s) wall (s) mem (MB) energy blkio-w (MB) blkio-r (MB) status score witness inspect witness cpu (s) wall (s) mem (MB) energy blkio-w (MB) blkio-r (MB) status score witness inspect witness cpu (s) wall (s) mem (MB) energy blkio-w (MB) blkio-r (MB)
bitvector/byte_add_false-unreach-call_true-no-overflow_true-termination.i false(unreach-call) 1 wit inspect 21 5.2 1200 140 .045  0     false(unreach-call) 1 wit inspect 5.2  2.9  260 0   0   false(unreach-call) 1 --- inspect 36   21   530 .71 0   false(unreach-call) 1 --- inspect 4.5  2.5  280 0   0   false(unreach-call) 1 --- inspect .69   .68   21    .10  0      - --- inspect - --- inspect
bitvector/sum02_false-unreach-call_true-no-overflow.i timeout 0 wit inspect 960 460   7300 9500 0      0     error (invalid witness file) 0 --- inspect .66 .40 43 0   0   error (invalid witness file) 0 --- inspect 6.1 3.3 260 .65 0   error (invalid witness file) 0 --- inspect .97 .62 50 0   0   error (invalid witness file) 0 --- inspect .0017 .0020 .39 0     0      - --- inspect - --- inspect
bitvector/byte_add_1_true-unreach-call_true-no-overflow_true-termination.i true 1 wit inspect 24 5.8 1300 160 0      0     - --- inspect - --- inspect - --- inspect - --- inspect unknown 0 wit inspect 12    6.5  450 0   0   timeout 0 --- inspect 960   920   980 .72 0  
bitvector/byte_add_2_true-unreach-call_true-no-overflow_true-termination.i true 1 wit inspect 23 5.4 1300 170 0      0     - --- inspect - --- inspect - --- inspect - --- inspect unknown 0 wit inspect 13    7.0  470 0   0   timeout 0 --- inspect 960   920   3200 .76 0  
bitvector/gcd_1_true-unreach-call_true-no-overflow.i true 2 wit inspect 16 5.8 1100 130 0      .090 - --- inspect - --- inspect - --- inspect - --- inspect true 2 wit inspect 9.7  7.5  330 0   0   timeout 0 --- inspect 960   940   3600 1.5  0  
bitvector/gcd_2_true-unreach-call_true-no-overflow.i true 2 wit inspect 150 140   1500 1700 0      0     - --- inspect - --- inspect - --- inspect - --- inspect true 2 wit inspect 160    150    560 0   0   timeout 0 --- inspect 960   950   620 .65 0  
bitvector/gcd_3_true-unreach-call_true-no-overflow.i true 2 wit inspect 130 120   1500 1200 0      0     - --- inspect - --- inspect - --- inspect - --- inspect true 2 wit inspect 130    130    570 0   0   timeout 0 --- inspect 960   950   1100 .67 0  
bitvector/gcd_4_true-unreach-call_true-no-overflow_true-termination.i true 2 wit inspect 11 3.5 1200 80 0      0     - --- inspect - --- inspect - --- inspect - --- inspect true 2 wit inspect 8.6  5.8  340 0   0   timeout 0 --- inspect 960   940   2000 .65 0  
bitvector/interleave_bits_true-unreach-call_true-no-overflow.i true 2 wit inspect 16 5.7 1300 130 0      0     - --- inspect - --- inspect - --- inspect - --- inspect true 2 wit inspect 14    10    580 0   0   error (7) 0 --- inspect 370   350   2300 .71 0  
bitvector/jain_1_true-unreach-call_true-no-overflow_false-termination.i true 2 wit inspect 13 3.7 1000 84 0      0     - --- inspect - --- inspect - --- inspect - --- inspect out of memory 0 --- inspect 820    810    7000 0   0   true 2 --- inspect 24   19   340 .62 0  
bitvector/jain_2_true-unreach-call_true-no-overflow_false-termination.i true 2 wit inspect 11 3.6 1200 88 0      0     - --- inspect - --- inspect - --- inspect - --- inspect out of memory 0 --- inspect 680    670    7000 0   0   true 2 --- inspect 20   16   330 .66 0  
bitvector/jain_4_true-unreach-call_true-no-overflow_false-termination.i true 2 wit inspect 11 3.5 1200 82 0      0     - --- inspect - --- inspect - --- inspect - --- inspect out of memory 0 --- inspect 550    540    7000 0   0   true 2 --- inspect 18   13   330 .66 0  
bitvector/jain_5_true-unreach-call_true-no-overflow.i timeout 0 wit inspect 910 870   6000 9700 0      0     - --- inspect - --- inspect - --- inspect - --- inspect out of memory 0 --- inspect 890    880    7000 0   0   timeout 0 --- inspect 960   940   670 .68 0  
bitvector/jain_6_true-unreach-call_true-no-overflow_false-termination.i true 2 wit inspect 13 3.8 1000 82 0      0     - --- inspect - --- inspect - --- inspect - --- inspect out of memory 0 --- inspect 560    550    7000 0   0   true 2 --- inspect 20   17   330 .62 0  
bitvector/jain_7_true-unreach-call_true-no-overflow_false-termination.i true 2 wit inspect 14 5.2 1100 120 0      0     - --- inspect - --- inspect - --- inspect - --- inspect out of memory 0 --- inspect 590    580    7000 0   0   true 2 --- inspect 120   120   430 .62 0  
bitvector/modulus_true-unreach-call_true-no-overflow.i true 2 wit inspect 34 12   1600 350 0      0     - --- inspect - --- inspect - --- inspect - --- inspect true 2 wit inspect 18    15    350 0   0   true 2 --- inspect 19   12   330 .75 0  
bitvector/num_conversion_1_true-unreach-call_true-no-overflow.i true 2 wit inspect 11 3.5 1200 86 0      0     - --- inspect - --- inspect - --- inspect - --- inspect true 2 wit inspect 6.3  3.5  290 0   0   true 2 --- inspect 32   21   560 .68 0  
bitvector/num_conversion_2_true-unreach-call_true-no-overflow.i true 1 wit inspect 16 4.2 1200 120 0      0     - --- inspect - --- inspect - --- inspect - --- inspect unknown 0 wit inspect 7.4  4.1  330 0   0   timeout 0 --- inspect 960   930   2200 .70 0  
bitvector/parity_true-unreach-call_true-no-overflow.i true 2 wit inspect 26 12   1300 250 0      0     - --- inspect - --- inspect - --- inspect - --- inspect true 2 wit inspect 32    23    500 0   0   timeout 0 --- inspect 960   950   1000 1.6  0  
bitvector/sum02_true-unreach-call_true-no-overflow.i timeout 0 wit inspect 970 460   7300 8000 0      0     - --- inspect - --- inspect - --- inspect - --- inspect error (invalid witness file) 0 --- inspect .81 .49 43 0   0   error (invalid witness file) 0 --- inspect 5.2 2.9 260 .65 0  
bitvector/s3_clnt_1_false-unreach-call_true-no-overflow.BV.c.cil.c false(unreach-call) 1 wit inspect 19 5.4 1300 160 .090  0     false(unreach-call) 1 wit inspect 7.1  3.8  300 0   0   false(unreach-call) 1 --- inspect 21   11   410 .71 0   unknown 0 --- inspect 5.7  3.1  290 0   0   true -32 --- inspect .76   .76   22    .16  0      - --- inspect - --- inspect
bitvector/s3_clnt_2_false-unreach-call_true-no-overflow.BV.c.cil.c false(unreach-call) 1 wit inspect 24 6.8 1400 180 .14   0     false(unreach-call) 1 wit inspect 8.3  4.4  320 0   0   false(unreach-call) 1 --- inspect 24   13   530 .68 0   unknown 0 --- inspect 5.6  3.1  280 0   0   true -32 --- inspect .80   .79   24    .15  .041  - --- inspect - --- inspect
bitvector/s3_clnt_3_false-unreach-call_true-no-overflow.BV.c.cil.c false(unreach-call) 1 wit inspect 19 5.5 1300 140 .078  0     false(unreach-call) 1 wit inspect 6.8  3.6  300 0   0   false(unreach-call) 1 --- inspect 26   14   420 .75 0   unknown 0 --- inspect 5.4  3.0  290 0   0   true -32 --- inspect .73   .73   22    .15  .041  - --- inspect - --- inspect
bitvector/s3_clnt_1_true-unreach-call_true-no-overflow.BV.c.cil.c true 2 wit inspect 20 5.7 1400 150 0      0     - --- inspect - --- inspect - --- inspect - --- inspect true 2 wit inspect 87    76    1100 0   0   true 2 --- inspect 52   30   810 .68 0  
bitvector/s3_clnt_2_true-unreach-call_true-no-overflow.BV.c.cil.c true 2 wit inspect 25 9.5 1200 200 0      0     - --- inspect - --- inspect - --- inspect - --- inspect true 2 wit inspect 21    13    620 0   0   true 2 --- inspect 50   28   900 .75 0  
bitvector/s3_clnt_3_true-unreach-call_true-no-overflow.BV.c.cil.c true 2 wit inspect 24 8.7 1500 200 0      0     - --- inspect - --- inspect - --- inspect - --- inspect true 2 wit inspect 15    8.7  570 0   0   true 2 --- inspect 37   20   800 .62 0  
bitvector/s3_srvr_1_alt_true-unreach-call_true-no-overflow.BV.c.cil.c timeout 0 wit inspect 930 450   4700 8700 .25   0     - --- inspect - --- inspect - --- inspect - --- inspect timeout 0 wit inspect 900    890    3800 0   0   timeout 0 --- inspect 960   900   4900 .65 0  
bitvector/s3_srvr_1_true-unreach-call_true-no-overflow.BV.c.cil.c true 2 wit inspect 21 6.9 1200 190 0      0     - --- inspect - --- inspect - --- inspect - --- inspect timeout 0 wit inspect 910    890    4600 0   0   true 2 --- inspect 51   28   980 .66 0  
bitvector/s3_srvr_2_alt_true-unreach-call_true-no-overflow_false-termination.BV.c.cil.c true 2 wit inspect 25 9.5 1500 210 0      0     - --- inspect - --- inspect - --- inspect - --- inspect timeout 0 wit inspect 900    890    4300 0   0   true 2 --- inspect 38   21   1000 .62 0  
bitvector/s3_srvr_2_true-unreach-call_true-no-overflow_false-termination.BV.c.cil.c true 2 wit inspect 26 9.4 1600 220 0      0     - --- inspect - --- inspect - --- inspect - --- inspect timeout 0 wit inspect 900    890    4300 0   0   true 2 --- inspect 35   20   920 .62 0  
bitvector/s3_srvr_3_alt_true-unreach-call_true-no-overflow.BV.c.cil.c true 2 wit inspect 19 5.6 1400 170 0      0     - --- inspect - --- inspect - --- inspect - --- inspect timeout 0 wit inspect 910    900    6200 0   0   true 2 --- inspect 40   23   910 .62 0  
bitvector/s3_srvr_3_true-unreach-call_true-no-overflow.BV.c.cil.c true 2 wit inspect 19 5.5 1400 160 0      0     - --- inspect - --- inspect - --- inspect - --- inspect timeout 0 wit inspect 910    890    5300 0   0   true 2 --- inspect 48   27   960 .62 0  
bitvector/soft_float_1_true-unreach-call_true-no-overflow_true-termination.c.cil.c true 2 wit inspect 21 8.5 1200 190 0      0     - --- inspect - --- inspect - --- inspect - --- inspect timeout 0 wit inspect 900    860    5000 0   0   true 2 --- inspect 140   110   770 .68 0  
bitvector/soft_float_2_true-unreach-call_true-no-overflow_true-termination.c.cil.c true 1 wit inspect 18 4.7 1200 130 0      0     - --- inspect - --- inspect - --- inspect - --- inspect timeout 0 wit inspect 900    870    3600 0   0   timeout 0 --- inspect 960   930   570 1.5  0  
bitvector/soft_float_3_true-unreach-call_true-no-overflow_true-termination.c.cil.c true 1 wit inspect 120 91   2100 1300 0      0     - --- inspect - --- inspect - --- inspect - --- inspect timeout 0 wit inspect 900    840    6800 0   0   timeout 0 --- inspect 960   890   840 .19 0  
bitvector/soft_float_4_true-unreach-call_true-no-overflow_true-termination.c.cil.c true 2 wit inspect 97 56   1700 960 0      0     - --- inspect - --- inspect - --- inspect - --- inspect true 2 wit inspect 120    110    560 0   0   false(unreach-call) -16 --- inspect 27   22   420 .66 0  
bitvector/soft_float_5_true-unreach-call_true-no-overflow_true-termination.c.cil.c true 1 wit inspect 16 4.3 1300 120 0      0     - --- inspect - --- inspect - --- inspect - --- inspect timeout 0 wit inspect 900    870    3700 0   0   timeout 0 --- inspect 960   930   580 1.6  0  
bitvector-regression/implicitfloatconversion_false-unreach-call_true-termination.c false(unreach-call) 1 wit inspect 12 3.7 1200 87 .0082 .090 false(unreach-call) 1 wit inspect 3.7  2.1  250 0   0   false(unreach-call) 1 --- inspect 13   7.9 290 .71 0   false(unreach-call) 1 --- inspect 3.5  2.0  240 0   0   false(unreach-call) 1 --- inspect .59   .59   20    .041 0      - --- inspect - --- inspect
bitvector-regression/implicitunsignedconversion_false-unreach-call_true-termination.c false(unreach-call) 1 wit inspect 13 3.9 1100 99 .0082 0     false(unreach-call) 1 wit inspect 3.6  2.0  250 0   0   false(unreach-call) 1 --- inspect 6.4 4.0 300 .62 0   false(unreach-call) 1 --- inspect 3.3  1.9  240 0   0   false(unreach-call) 1 --- inspect .57   .59   20    .041 0      - --- inspect - --- inspect
bitvector-regression/integerpromotion_false-unreach-call_true-termination.c false(unreach-call) 1 wit inspect 12 3.7 1200 88 .0082 0     false(unreach-call) 1 wit inspect 4.2  2.3  250 0   0   false(unreach-call) 1 --- inspect 12   7.4 290 .71 0   false(unreach-call) 1 --- inspect 3.6  2.1  250 0   0   false(unreach-call) 1 --- inspect .58   .60   20    .041 0      - --- inspect - --- inspect
bitvector-regression/recHanoi03_false-unreach-call_true-termination.c false(unreach-call) 1 wit inspect 74 55   1700 800 0      0     false(unreach-call) 1 wit inspect 7.0  3.7  300 0   0   false(unreach-call) 1 --- inspect 43   27   1200 .68 0   false(unreach-call) 1 --- inspect 5.1  2.8  260 0   0   false(unreach-call) 1 --- inspect .62   .62   21    .049 .0041 - --- inspect - --- inspect
bitvector-regression/signextension2_false-unreach-call_true-termination.c false(unreach-call) 1 wit inspect 12 3.7 1200 91 .0082 0     false(unreach-call) 1 wit inspect 3.7  2.1  250 0   0   true -32 --- inspect 6.4 3.6 290 .66 0   false(unreach-call) 1 --- inspect 3.5  2.0  250 0   0   false(unreach-call) 1 --- inspect .58   .58   20    .045 0      - --- inspect - --- inspect
bitvector-regression/signextension_false-unreach-call_true-termination.c false(unreach-call) 1 wit inspect 13 3.9 1100 96 .0082 .090 false(unreach-call) 1 wit inspect 4.4  2.4  250 0   0   true -32 --- inspect 6.8 3.9 300 .66 0   false(unreach-call) 1 --- inspect 3.5  2.0  240 0   0   false(unreach-call) 1 --- inspect .60   .60   20    .045 0      - --- inspect - --- inspect
bitvector-regression/implicitunsignedconversion_true-unreach-call_true-termination.c true 2 wit inspect 12 3.5 1000 81 0      0     - --- inspect - --- inspect - --- inspect - --- inspect true 2 wit inspect 4.7  2.6  250 0   0   true 2 --- inspect 8.6 5.0 310 .66 0  
bitvector-regression/integerpromotion_true-unreach-call_true-termination.c true 2 wit inspect 13 3.6 1000 79 0      0     - --- inspect - --- inspect - --- inspect - --- inspect true 2 wit inspect 3.4  1.9  250 0   0   true 2 --- inspect 13   7.9 290 .75 0  
bitvector-regression/signextension2_true-unreach-call_true-termination.c true 2 wit inspect 11 3.5 1200 83 0      0     - --- inspect - --- inspect - --- inspect - --- inspect true 2 wit inspect 4.1  2.3  250 0   0   true 2 --- inspect 7.5 4.2 310 .66 0  
bitvector-regression/signextension_true-unreach-call_true-termination.c true 2 wit inspect 13 3.7 1000 91 0      0     - --- inspect - --- inspect - --- inspect - --- inspect true 2 wit inspect 4.5  2.5  250 0   0   true 2 --- inspect 7.6 4.4 310 .66 0  
bitvector-loops/diamond_false-unreach-call2.i false(unreach-call) 1 wit inspect 13 3.8 1200 100 .016  0     false(unreach-call) 1 wit inspect 4.2  2.3  260 0   0   false(unreach-call) 1 --- inspect 8.3 5.0 310 .62 0   false(unreach-call) 1 --- inspect 4.6  2.6  250 0   0   false(unreach-call) 1 --- inspect .58   .58   21    .049 0      - --- inspect - --- inspect
bitvector-loops/overflow_false-unreach-call1.i timeout 0 wit inspect 970 490   7600 8900 0      0     error (invalid witness file) 0 --- inspect .82 .50 42 0   0   error (invalid witness file) 0 --- inspect 5.4 3.0 270 .65 0   error (invalid witness file) 0 --- inspect 1.1  .72 50 0   0   error (invalid witness file) 0 --- inspect .0018 .0023 .53 0     0      - --- inspect - --- inspect
bitvector-loops/verisec_sendmail__tTflag_arr_one_loop_false-unreach-call_true-termination.i false(unreach-call) 1 wit inspect 22 7.6 1300 170 .041  0     false(unreach-call) 1 wit inspect 6.8  3.8  280 0   0   timeout 0 --- inspect 97   85   1200 1.6  0   false(unreach-call) 1 --- inspect 4.3  2.5  260 0   0   false(unreach-call) 1 --- inspect .63   .63   21    .061 0      - --- inspect - --- inspect
sv-benchmarks/c/ status score witness inspect witness cpu (s) wall (s) mem (MB) energy (J) blkio-w (MB) blkio-r (MB) status score witness inspect witness cpu (s) wall (s) mem (MB) energy blkio-w (MB) blkio-r (MB) status score witness inspect witness cpu (s) wall (s) mem (MB) energy blkio-w (MB) blkio-r (MB) status score witness inspect witness cpu (s) wall (s) mem (MB) energy blkio-w (MB) blkio-r (MB) status score witness inspect witness cpu (s) wall (s) mem (MB) energy blkio-w (MB) blkio-r (MB) status score witness inspect witness cpu (s) wall (s) mem (MB) energy blkio-w (MB) blkio-r (MB) status score witness inspect witness cpu (s) wall (s) mem (MB) energy blkio-w (MB) blkio-r (MB)
total 50 72 6000 3400 91000 56000 .70 .27  14 12 66 36 3400 0   0   14 -55 310 210   6600 10   0   14 9 55 31 3200 0   0   14 -87 7.7 7.7 250 .94 .086  36 32 14000 13000 98000 0   0   36 24 14000 13000 37000 27    0  
    correct results 39 66 1100 570 50000 9500 .45 .27  12 12 65 35 3300 0   0   9 9 190 110   4200 6.2 0   9 9 36 21 2300 0   0   9 9 5.4 5.5 180 .48 .0041 16 32 630 570 7300 0   0   20 40 780 550 12000 13    0  
        correct true 27 54 800 460 34000 7400 0    .090 0 0 0 0 16 32 630 570 7300 0   0   20 40 780 550 12000 13    0  
        correct false 12 12 250 110 15000 2100 .45 .18  12 12 65 35 3300 0   0   9 9 190 110   4200 6.2 0   9 9 36 21 2300 0   0   9 9 5.4 5.5 180 .48 .0041 0 0
    correct-unconfimed results 6 6 220 120 8400 2000 0    0     0 0 0 0 0 0
        correct-unconfirmed true 6 6 220 120 8400 2000 0    0     0 0 0 0 0 0
        correct-unconfirmed false 0 0 0 0 0 0 0
    incorrect results 0 0 2 -64 13 7.5 590 1.3 0   0 3 -96 2.3 2.3 68 .46 .082  0 1 -16 27 22 420 .66 0  
        incorrect true 0 0 2 -64 13 7.5 590 1.3 0   0 3 -96 2.3 2.3 68 .46 .082  0 0
        incorrect false 0 0 0 0 0 0 1 -16 27 22 420 .66 0  
score (50 tasks, max score: 86) 72 12 -55 9 -87 32 24
Run set pesco.sv-comp19_prop-reachsafety.ReachSafety-BitVectors cpa-seq-validate-violation-witnesses-pesco.sv-comp19_prop-reachsafety.ReachSafety-BitVectors uautomizer-validate-violation-witnesses-pesco.sv-comp19_prop-reachsafety.ReachSafety-BitVectors cpa-witness2test-validate-violation-witnesses-pesco.sv-comp19_prop-reachsafety.ReachSafety-BitVectors fshell-witness2test-validate-violation-witnesses-pesco.sv-comp19_prop-reachsafety.ReachSafety-BitVectors cpa-seq-validate-correctness-witnesses-pesco.sv-comp19_prop-reachsafety.ReachSafety-BitVectors uautomizer-validate-correctness-witnesses-pesco.sv-comp19_prop-reachsafety.ReachSafety-BitVectors