Tool Map2Check v7.2-Flock : Tue Nov 27 22:00:00 -04 2018 CPAchecker 1.7-svn 29852 ULTIMATE Automizer 0.1.23-635dfa2a CPA-witness2test 1.7-svn 29852 CProver witness2test 0.1 CPAchecker 1.7-svn 29852 ULTIMATE Automizer 0.1.23-635dfa2a
Limits timelimit: 900 s, memlimit: 15000 MB, CPU core limit: 8 timelimit: 90 s, memlimit: 7000 MB, CPU core limit: 2 timelimit: 900 s, memlimit: 7000 MB, CPU core limit: 2
Host apollon* [apollon053; apollon130] apollon*
OS Linux 4.15.0-42-generic
System CPU: Intel Xeon E3-1230 v5 @ 3.40 GHz, cores: 8, frequency: 3.8 GHz, Turbo Boost: disabled; RAM: 33546 MB
Date of execution 2018-12-06 12:20:21 CET 2018-12-07 01:02:57 CET 2018-12-07 02:56:49 CET 2018-12-07 03:56:35 CET 2018-12-12 20:36:04 CET 2018-12-07 00:06:42 CET 2018-12-07 01:25:40 CET
Run set map2check.sv-comp19_prop-reachsafety.ReachSafety-BitVectors cpa-seq-validate-violation-witnesses-map2check.sv-comp19_prop-reachsafety.ReachSafety-BitVectors uautomizer-validate-violation-witnesses-map2check.sv-comp19_prop-reachsafety.ReachSafety-BitVectors cpa-witness2test-validate-violation-witnesses-map2check.sv-comp19_prop-reachsafety.ReachSafety-BitVectors fshell-witness2test-validate-violation-witnesses-map2check.sv-comp19_prop-reachsafety.ReachSafety-BitVectors cpa-seq-validate-correctness-witnesses-map2check.sv-comp19_prop-reachsafety.ReachSafety-BitVectors uautomizer-validate-correctness-witnesses-map2check.sv-comp19_prop-reachsafety.ReachSafety-BitVectors
Options -witnessValidation -setprop witness.checkProgramHash=false -heap 5000m -benchmark -setprop cpa.predicate.memoryAllocationsAlwaysSucceed=true -setprop cpa.smg.memoryAllocationFunctions=malloc,__kmalloc,kmalloc,kzalloc,kzalloc_node,ldv_zalloc,ldv_malloc -setprop cpa.smg.arrayAllocationFunctions=calloc,kmalloc_array,kcalloc -setprop cpa.smg.zeroingMemoryAllocation=calloc,kzalloc,kcalloc,kzalloc_node,ldv_zalloc -setprop cpa.smg.deallocationFunctions=free,kfree,kfree_const -witness ../../results-verified/map2check.2018-12-06_1220.logfiles/${rundefinition_name}.${inputfile_name}.files/witness.graphml --full-output --validate ../../results-verified/map2check.2018-12-06_1220.logfiles/${rundefinition_name}.${inputfile_name}.files/witness.graphml -setprop witness.checkProgramHash=false -heap 5000m -benchmark -setprop analysis.summaryEdges=true -setprop cpa.callstack.skipVoidRecursion=true -setprop cpa.callstack.skipFunctionPointerRecursion=true -witness ../../results-verified/map2check.2018-12-06_1220.logfiles/${rundefinition_name}.${inputfile_name}.files/witness.graphml --graphml-witness ../../results-verified/map2check.2018-12-06_1220.logfiles/${rundefinition_name}.${inputfile_name}.files/witness.graphml -witnessValidation -setprop witness.checkProgramHash=false -heap 5000m -benchmark -setprop cpa.predicate.memoryAllocationsAlwaysSucceed=true -witness ../../results-verified/map2check.2018-12-06_1220.logfiles/${rundefinition_name}.${inputfile_name}.files/witness.graphml --full-output --validate ../../results-verified/map2check.2018-12-06_1220.logfiles/${rundefinition_name}.${inputfile_name}.files/witness.graphml
sv-benchmarks/c/ status score witness inspect witness cpu (s) wall (s) mem (MB) energy (J) blkio-w (MB) blkio-r (MB) status score witness inspect witness cpu (s) wall (s) mem (MB) energy blkio-w (MB) blkio-r (MB) status score witness inspect witness cpu (s) wall (s) mem (MB) energy blkio-w (MB) blkio-r (MB) status score witness inspect witness cpu (s) wall (s) mem (MB) energy blkio-w (MB) blkio-r (MB) status score witness inspect witness cpu (s) wall (s) mem (MB) energy blkio-w (MB) blkio-r (MB) status score witness inspect witness cpu (s) wall (s) mem (MB) energy blkio-w (MB) blkio-r (MB) status score witness inspect witness cpu (s) wall (s) mem (MB) energy blkio-w (MB) blkio-r (MB)
bitvector/byte_add_false-unreach-call_true-no-overflow_true-termination.i 1 140    140    110 1800   .029  0      -32 12    6.1  440 0   0   -32 7.1   4.4   310   .66 0   0 3.8  2.1  250 0   0   1 .59   .59   20    .057 .0041 - -
bitvector/sum02_false-unreach-call_true-no-overflow.i 1 5.4  4.6  82 61   .020  0      0 97    80    2000 0   0   0 18     14     330   .62 0   0 3.5  2.0  250 0   0   1 1.0    1.0    20    .045 0      - -
bitvector/byte_add_1_true-unreach-call_true-no-overflow_true-termination.i 0 1.6  1.3  49 17   0      0      - - - - 0 .75 .46 40 0   0   0 .020 .020 5.6 0    0  
bitvector/byte_add_2_true-unreach-call_true-no-overflow_true-termination.i 0 1.5  1.3  48 22   0      0      - - - - 0 .75 .47 40 0   0   0 .021 .022 5.7 0    0  
bitvector/gcd_1_true-unreach-call_true-no-overflow.i 2 3.2  3.1  75 41   .012  0      - - - - 2 12    9.9  320 0   0   0 960     950     660   .67 0  
bitvector/gcd_2_true-unreach-call_true-no-overflow.i 0 900    460    4200 8900   28000      .0082 - - - - 0 .71 .42 42 0   0   0 .020 .021 5.6 0    0  
bitvector/gcd_3_true-unreach-call_true-no-overflow.i 0 900    460    4300 11000   28000      .0082 - - - - 0 .61 .38 42 0   0   0 .020 .021 5.6 0    0  
bitvector/gcd_4_true-unreach-call_true-no-overflow_true-termination.i 0 900    470    85 12000   29000      0      - - - - 0 .75 .46 41 0   0   0 .021 .022 5.6 0    0  
bitvector/interleave_bits_true-unreach-call_true-no-overflow.i 0 900    460    4200 10000   28000      .0082 - - - - 0 .79 .48 41 0   0   0 .019 .020 5.6 0    0  
bitvector/jain_1_true-unreach-call_true-no-overflow_false-termination.i 0 900    850    4600 9100   .029  0      - - - - 0 .77 .47 40 0   0   0 .021 .022 5.7 0    0  
bitvector/jain_2_true-unreach-call_true-no-overflow_false-termination.i 0 900    850    4300 9000   .025  0      - - - - 0 .66 .39 41 0   0   0 .022 .022 5.6 0    0  
bitvector/jain_4_true-unreach-call_true-no-overflow_false-termination.i 0 900    850    4700 11000   .029  0      - - - - 0 .61 .38 42 0   0   0 .027 .029 5.7 0    0  
bitvector/jain_5_true-unreach-call_true-no-overflow.i 0 900    450    75 8400   .012  0      - - - - 0 .69 .44 40 0   0   0 .021 .021 5.6 0    0  
bitvector/jain_6_true-unreach-call_true-no-overflow_false-termination.i 0 900    850    5300 11000   .029  0      - - - - 0 .61 .37 42 0   0   0 .021 .021 5.6 0    0  
bitvector/jain_7_true-unreach-call_true-no-overflow_false-termination.i 0 900    850    4200 11000   .016  0      - - - - 0 .57 .36 41 0   0   0 .026 .026 5.6 0    0  
bitvector/modulus_true-unreach-call_true-no-overflow.i 0 900    610    4300 10000   7200      .0041 - - - - 0 .68 .41 40 0   0   0 .020 .020 5.6 0    0  
bitvector/num_conversion_1_true-unreach-call_true-no-overflow.i 0 900    480    85 11000   30000      .0082 - - - - 0 .79 .49 41 0   0   0 .020 .022 5.6 0    0  
bitvector/num_conversion_2_true-unreach-call_true-no-overflow.i 0 900    470    2100 9700   27000      .0082 - - - - 0 .76 .46 40 0   0   0 .022 .022 5.6 0    0  
bitvector/parity_true-unreach-call_true-no-overflow.i 0 900    450    2100 11000   28000      .0082 - - - - 0 .60 .38 41 0   0   0 .020 .021 5.6 0    0  
bitvector/sum02_true-unreach-call_true-no-overflow.i 0 900    450    75 10000   .58   0      - - - - 0 .77 .48 41 0   0   0 .021 .022 5.6 0    0  
bitvector/s3_clnt_1_false-unreach-call_true-no-overflow.BV.c.cil.c 0 900    880    2200 7600   2200      .0082 0 .63 .39 42 0   0   0 .021 .021 5.6 0    0   0 .94 .61 47 0   0   0 .0022 .0029 .54 0     0      - -
bitvector/s3_clnt_2_false-unreach-call_true-no-overflow.BV.c.cil.c 0 900    860    4300 6500   2200      .0082 0 .58 .36 41 0   0   0 .021 .021 5.6 0    0   0 .94 .60 48 0   0   0 .0039 .0049 .53 0     0      - -
bitvector/s3_clnt_3_false-unreach-call_true-no-overflow.BV.c.cil.c 0 900    900    2300 5400   1.6    0      0 .60 .37 41 0   0   0 .021 .021 5.6 0    0   0 .96 .62 47 0   0   0 .0055 .0076 .53 0     0      - -
bitvector/s3_clnt_1_true-unreach-call_true-no-overflow.BV.c.cil.c 0 900    860    4300 7300   2400      .0082 - - - - 0 .67 .41 40 0   0   0 .021 .022 5.6 0    0  
bitvector/s3_clnt_2_true-unreach-call_true-no-overflow.BV.c.cil.c 0 900    860    4400 8100   2200      .0082 - - - - 0 .61 .37 40 0   0   0 .021 .023 5.6 0    0  
bitvector/s3_clnt_3_true-unreach-call_true-no-overflow.BV.c.cil.c 0 900    900    2300 8200   1.4    .13   - - - - 0 .73 .45 40 0   0   0 .022 .023 5.6 0    0  
bitvector/s3_srvr_1_alt_true-unreach-call_true-no-overflow.BV.c.cil.c 0 900    850    4400 6500   2400      .0082 - - - - 0 .73 .44 41 0   0   0 .020 .021 5.6 0    0  
bitvector/s3_srvr_1_true-unreach-call_true-no-overflow.BV.c.cil.c 0 900    850    4300 7000   2500      .0082 - - - - 0 .58 .36 40 0   0   0 .021 .022 5.6 0    0  
bitvector/s3_srvr_2_alt_true-unreach-call_true-no-overflow_false-termination.BV.c.cil.c 0 900    860    4400 7700   2100      .0082 - - - - 0 .66 .40 43 0   0   0 .020 .020 5.6 0    0  
bitvector/s3_srvr_2_true-unreach-call_true-no-overflow_false-termination.BV.c.cil.c 0 900    860    4300 6300   1800      .0082 - - - - 0 .62 .38 41 0   0   0 .021 .021 5.6 0    0  
bitvector/s3_srvr_3_alt_true-unreach-call_true-no-overflow.BV.c.cil.c 0 900    860    4300 9300   2100      .0082 - - - - 0 .60 .37 40 0   0   0 .020 .021 5.6 0    0  
bitvector/s3_srvr_3_true-unreach-call_true-no-overflow.BV.c.cil.c 0 900    860    4400 7200   2100      0      - - - - 0 .65 .39 42 0   0   0 .020 .022 5.6 0    0  
bitvector/soft_float_1_true-unreach-call_true-no-overflow_true-termination.c.cil.c 0 900    660    4300 10000   13000      .0041 - - - - 0 .66 .42 41 0   0   0 .019 .020 5.6 0    0  
bitvector/soft_float_2_true-unreach-call_true-no-overflow_true-termination.c.cil.c 0 900    650    4300 9600   14000      .0082 - - - - 0 .62 .39 42 0   0   0 .021 .022 5.6 0    0  
bitvector/soft_float_3_true-unreach-call_true-no-overflow_true-termination.c.cil.c 0 900    900    610 12000   40      0      - - - - 0 .61 .37 40 0   0   0 .020 .021 5.8 0    0  
bitvector/soft_float_4_true-unreach-call_true-no-overflow_true-termination.c.cil.c 0 900    640    4300 10000   14000      .0082 - - - - 0 .75 .46 42 0   0   0 .021 .022 5.6 0    0  
bitvector/soft_float_5_true-unreach-call_true-no-overflow_true-termination.c.cil.c 0 900    650    4300 9000   14000      0      - - - - 0 .65 .40 42 0   0   0 .020 .021 5.6 0    0  
bitvector-regression/implicitfloatconversion_false-unreach-call_true-termination.c 1 .42 .41 83 6.1 .0082 0      1 3.7  2.0  250 0   0   1 14     7.5   310   .68 0   1 3.4  2.0  250 0   0   1 .56   .56   20    .041 0      - -
bitvector-regression/implicitunsignedconversion_false-unreach-call_true-termination.c 1 .43 .41 83 5.9 .0082 0      1 3.5  2.0  250 0   0   1 6.6   4.2   290   .66 0   1 3.5  2.0  250 0   0   1 .59   .59   20    .041 0      - -
bitvector-regression/integerpromotion_false-unreach-call_true-termination.c 1 .44 .42 83 4.5 .0082 0      1 3.4  1.9  250 0   0   1 14     8.3   300   .75 0   1 3.4  2.0  240 0   0   1 .56   .56   20    .041 0      - -
bitvector-regression/recHanoi03_false-unreach-call_true-termination.c 0 900    900    1800 10000   .14   0      0 .62 .38 41 0   0   0 .026 .027 5.6 0    0   0 .93 .60 47 0   0   0 .0048 .0064 .52 0     0      - -
bitvector-regression/signextension2_false-unreach-call_true-termination.c 1 .44 .43 83 4.5 .0082 0      1 3.5  1.9  250 0   0   1 7.0   4.4   300   .66 0   1 3.4  2.0  250 0   0   1 .56   .56   20    .045 .0041 - -
bitvector-regression/signextension_false-unreach-call_true-termination.c 1 .41 .40 83 4.6 .0082 0      1 3.5  2.0  250 0   0   1 6.6   3.8   310   .66 0   1 3.5  2.0  240 0   0   1 .62   .62   20    .045 0      - -
bitvector-regression/implicitunsignedconversion_true-unreach-call_true-termination.c 0 900    480    85 9500   30000      .0082 - - - - 0 .74 .45 40 0   0   0 .020 .021 5.7 0    0  
bitvector-regression/integerpromotion_true-unreach-call_true-termination.c 0 900    480    84 9700   30000      .0041 - - - - 0 .75 .46 41 0   0   0 .023 .024 5.7 0    0  
bitvector-regression/signextension2_true-unreach-call_true-termination.c 0 900    480    85 10000   29000      .0082 - - - - 0 .69 .42 41 0   0   0 .040 .044 5.6 0    0  
bitvector-regression/signextension_true-unreach-call_true-termination.c 0 900    480    85 11000   29000      .0082 - - - - 0 .58 .35 40 0   0   0 .021 .022 5.8 0    0  
bitvector-loops/diamond_false-unreach-call2.i 1 .44 .42 83 4.9 .037  0      -32 4.4  2.4  250 0   0   -32 7.5   4.7   310   .66 0   0 3.4  2.0  240 0   0   1 .59   .59   20    .049 0      - -
bitvector-loops/overflow_false-unreach-call1.i 1 .42 .40 83 5.0 .0082 0      0 98    87    1700 0   0   -32 8.5   4.8   320   .62 0   1 6.9  5.5  240 0   0   1 4.3    4.3    20    .045 0      - -
bitvector-loops/verisec_sendmail__tTflag_arr_one_loop_false-unreach-call_true-termination.i 1 .57 .51 84 5.8 4.2    0      0 92    88    780 0   0   -32 12     6.7   400   .66 0   1 3.8  2.2  250 0   0   1 .58   .58   20    .049 0      - -
sv-benchmarks/c/ status score witness inspect witness cpu (s) wall (s) mem (MB) energy (J) blkio-w (MB) blkio-r (MB) status score witness inspect witness cpu (s) wall (s) mem (MB) energy blkio-w (MB) blkio-r (MB) status score witness inspect witness cpu (s) wall (s) mem (MB) energy blkio-w (MB) blkio-r (MB) status score witness inspect witness cpu (s) wall (s) mem (MB) energy blkio-w (MB) blkio-r (MB) status score witness inspect witness cpu (s) wall (s) mem (MB) energy blkio-w (MB) blkio-r (MB) status score witness inspect witness cpu (s) wall (s) mem (MB) energy blkio-w (MB) blkio-r (MB) status score witness inspect witness cpu (s) wall (s) mem (MB) energy blkio-w (MB) blkio-r (MB)
total 50 12 33000   26000   110000 340000 400000     .30 14 -59 320 270   6500 0   0   14 -123 100 63 3200 6.6 0   14 7 42 26 2600 0   0   14 10 10   10   210 .46 .0082 36 2 36 24   1800 0   0   36 0 960 950 860 .67 0  
    correct results 11 12 150   150   930 2000 4.3   0    5 5 18 9.8 1200 0   0   5 5 48 28 1500 3.4 0   7 7 28 18 1700 0   0   10 10 10   10   200 .46 .0082 1 2 12 9.9 320 0   0   0
        correct true 1 2 3.2 3.1 75 41 .012 0    0 0 0 0 1 2 12 9.9 320 0   0   0
        correct false 10 10 150   150   860 1900 4.3   0    5 5 18 9.8 1200 0   0   5 5 48 28 1500 3.4 0   7 7 28 18 1700 0   0   10 10 10   10   200 .46 .0082 0 0
    incorrect results 0 2 -64 16 8.6 680 0   0   4 -128 35 21 1300 2.6 0   0 0 0 0
        incorrect true 0 2 -64 16 8.6 680 0   0   4 -128 35 21 1300 2.6 0   0 0 0 0
        incorrect false 0 0 0 0 0 0 0
score (50 tasks, max score: 86) 12 -59 -123 7 10 2 0
Run set map2check.sv-comp19_prop-reachsafety.ReachSafety-BitVectors cpa-seq-validate-violation-witnesses-map2check.sv-comp19_prop-reachsafety.ReachSafety-BitVectors uautomizer-validate-violation-witnesses-map2check.sv-comp19_prop-reachsafety.ReachSafety-BitVectors cpa-witness2test-validate-violation-witnesses-map2check.sv-comp19_prop-reachsafety.ReachSafety-BitVectors fshell-witness2test-validate-violation-witnesses-map2check.sv-comp19_prop-reachsafety.ReachSafety-BitVectors cpa-seq-validate-correctness-witnesses-map2check.sv-comp19_prop-reachsafety.ReachSafety-BitVectors uautomizer-validate-correctness-witnesses-map2check.sv-comp19_prop-reachsafety.ReachSafety-BitVectors