Tool DepthK 3.1 CPAchecker 1.7-svn 29852 ULTIMATE Automizer 0.1.23-635dfa2a CPA-witness2test 1.7-svn 29852 CProver witness2test 0.1 CPAchecker 1.7-svn 29852 ULTIMATE Automizer 0.1.23-635dfa2a
Limits timelimit: 900 s, memlimit: 15000 MB, CPU core limit: 8 timelimit: 90 s, memlimit: 7000 MB, CPU core limit: 2 timelimit: 900 s, memlimit: 7000 MB, CPU core limit: 2
Host apollon* [apollon001; apollon005; apollon039; apollon053; apollon087; apollon091] [apollon007; apollon009; apollon073; apollon078] apollon*
OS Linux 4.15.0-42-generic
System CPU: Intel Xeon E3-1230 v5 @ 3.40 GHz, cores: 8, frequency: 3.8 GHz, Turbo Boost: disabled; RAM: 33546 MB
Date of execution 2018-12-05 09:36:33 CET 2018-12-06 10:02:56 CET 2018-12-06 11:08:44 CET 2018-12-06 11:42:46 CET 2018-12-12 19:35:41 CET 2018-12-06 09:26:28 CET 2018-12-06 10:24:56 CET
Run set depthk.sv-comp19_prop-reachsafety.ReachSafety-BitVectors cpa-seq-validate-violation-witnesses-depthk.sv-comp19_prop-reachsafety.ReachSafety-BitVectors uautomizer-validate-violation-witnesses-depthk.sv-comp19_prop-reachsafety.ReachSafety-BitVectors cpa-witness2test-validate-violation-witnesses-depthk.sv-comp19_prop-reachsafety.ReachSafety-BitVectors fshell-witness2test-validate-violation-witnesses-depthk.sv-comp19_prop-reachsafety.ReachSafety-BitVectors cpa-seq-validate-correctness-witnesses-depthk.sv-comp19_prop-reachsafety.ReachSafety-BitVectors uautomizer-validate-correctness-witnesses-depthk.sv-comp19_prop-reachsafety.ReachSafety-BitVectors
Options -witnessValidation -setprop witness.checkProgramHash=false -heap 5000m -benchmark -setprop cpa.predicate.memoryAllocationsAlwaysSucceed=true -setprop cpa.smg.memoryAllocationFunctions=malloc,__kmalloc,kmalloc,kzalloc,kzalloc_node,ldv_zalloc,ldv_malloc -setprop cpa.smg.arrayAllocationFunctions=calloc,kmalloc_array,kcalloc -setprop cpa.smg.zeroingMemoryAllocation=calloc,kzalloc,kcalloc,kzalloc_node,ldv_zalloc -setprop cpa.smg.deallocationFunctions=free,kfree,kfree_const -witness ../../results-verified/depthk.2018-12-05_0936.logfiles/${rundefinition_name}.${inputfile_name}.files/witness.graphml --full-output --validate ../../results-verified/depthk.2018-12-05_0936.logfiles/${rundefinition_name}.${inputfile_name}.files/witness.graphml -setprop witness.checkProgramHash=false -heap 5000m -benchmark -setprop analysis.summaryEdges=true -setprop cpa.callstack.skipVoidRecursion=true -setprop cpa.callstack.skipFunctionPointerRecursion=true -witness ../../results-verified/depthk.2018-12-05_0936.logfiles/${rundefinition_name}.${inputfile_name}.files/witness.graphml --graphml-witness ../../results-verified/depthk.2018-12-05_0936.logfiles/${rundefinition_name}.${inputfile_name}.files/witness.graphml -witnessValidation -setprop witness.checkProgramHash=false -heap 5000m -benchmark -setprop cpa.predicate.memoryAllocationsAlwaysSucceed=true -witness ../../results-verified/depthk.2018-12-05_0936.logfiles/${rundefinition_name}.${inputfile_name}.files/witness.graphml --full-output --validate ../../results-verified/depthk.2018-12-05_0936.logfiles/${rundefinition_name}.${inputfile_name}.files/witness.graphml
sv-benchmarks/c/ status score witness inspect witness cpu (s) wall (s) mem (MB) energy (J) blkio-w (MB) blkio-r (MB) status score witness inspect witness cpu (s) wall (s) mem (MB) energy blkio-w (MB) blkio-r (MB) status score witness inspect witness cpu (s) wall (s) mem (MB) energy blkio-w (MB) blkio-r (MB) status score witness inspect witness cpu (s) wall (s) mem (MB) energy blkio-w (MB) blkio-r (MB) status score witness inspect witness cpu (s) wall (s) mem (MB) energy blkio-w (MB) blkio-r (MB) status score witness inspect witness cpu (s) wall (s) mem (MB) energy blkio-w (MB) blkio-r (MB) status score witness inspect witness cpu (s) wall (s) mem (MB) energy blkio-w (MB) blkio-r (MB)
bitvector/byte_add_false-unreach-call_true-no-overflow_true-termination.i 1 .74 .73 36 8.9 62    0      1 5.9  3.2  250 0   0   1 47     29     630   .68 0   1 4.1  2.4  250 0   0   1 .59   .59   20    .057 0      - -
bitvector/sum02_false-unreach-call_true-no-overflow.i 0 160    160    81 2300   3000    .0082 0 .71 .44 40 0   0   0 .021 .023 5.7 0    0   0 .94 .60 48 0   0   0 .0023 .0033 .52 0     0      - -
bitvector/byte_add_1_true-unreach-call_true-no-overflow_true-termination.i 0 2.3  2.0  68 27   150    0      - - - - 2 10    5.3  370 0   0   0 960     930     1000   .69 0  
bitvector/byte_add_2_true-unreach-call_true-no-overflow_true-termination.i 0 2.3  2.1  67 28   150    0      - - - - 2 9.4  5.1  370 0   0   0 960     930     1100   .71 0  
bitvector/gcd_1_true-unreach-call_true-no-overflow.i 0 5.3  5.1  75 67   27    0      - - - - 2 13    10    320 0   0   0 960     940     3800   1.0  0  
bitvector/gcd_2_true-unreach-call_true-no-overflow.i 0 65    64    77 890   300    0      - - - - 2 140    130    560 0   0   0 960     950     630   .63 0  
bitvector/gcd_3_true-unreach-call_true-no-overflow.i 0 67    66    76 840   300    0      - - - - 2 120    120    560 0   0   0 960     950     1700   .62 0  
bitvector/gcd_4_true-unreach-call_true-no-overflow_true-termination.i 0 3.8  3.5  68 48   130    .0041 - - - - 2 7.1  4.6  320 0   0   2 37     28     590   .62 0  
bitvector/interleave_bits_true-unreach-call_true-no-overflow.i 0 4.9  4.6  68 59   420    .0041 - - - - 2 11    7.7  390 0   0   2 210     190     630   .68 0  
bitvector/jain_1_true-unreach-call_true-no-overflow_false-termination.i 0 900    900    310 10000   1400    .020  - - - - 0 .62 .37 40 0   0   0 .023 .026 5.6 0    0  
bitvector/jain_2_true-unreach-call_true-no-overflow_false-termination.i 0 900    900    280 10000   1300    .0082 - - - - 0 .61 .37 42 0   0   0 .020 .021 5.6 0    0  
bitvector/jain_4_true-unreach-call_true-no-overflow_false-termination.i 0 900    900    260 11000   1300    .012  - - - - 0 .61 .39 41 0   0   0 .024 .025 5.6 0    0  
bitvector/jain_5_true-unreach-call_true-no-overflow.i 0 93    92    55 1100   3000    .033  - - - - 0 .59 .36 42 0   0   0 .021 .023 5.6 0    0  
bitvector/jain_6_true-unreach-call_true-no-overflow_false-termination.i 0 900    900    300 11000   1200    0      - - - - 0 .59 .36 40 0   0   0 .024 .026 5.7 0    0  
bitvector/jain_7_true-unreach-call_true-no-overflow_false-termination.i 0 900    900    280 12000   2900    .016  - - - - 0 .73 .46 40 0   0   0 .020 .024 5.6 0    0  
bitvector/modulus_true-unreach-call_true-no-overflow.i 0 8.9  8.6  160 92   31    0      - - - - 2 18    16    340 0   0   2 15     9.8   380   .62 0  
bitvector/num_conversion_1_true-unreach-call_true-no-overflow.i 0 2.3  2.0  68 28   240    .0041 - - - - 2 5.4  2.9  280 0   0   2 34     22     550   .68 0  
bitvector/num_conversion_2_true-unreach-call_true-no-overflow.i 0 2.2  2.0  68 28   240    0      - - - - 2 5.6  3.1  290 0   0   0 960     930     2200   .69 0  
bitvector/parity_true-unreach-call_true-no-overflow.i 0 24    23    68 300   970    .012  - - - - 2 31    23    470 0   0   0 960     950     1000   .70 0  
bitvector/sum02_true-unreach-call_true-no-overflow.i 0 170    170    85 2000   3000    .012  - - - - 0 .60 .36 40 0   0   0 .024 .024 5.6 0    0  
bitvector/s3_clnt_1_false-unreach-call_true-no-overflow.BV.c.cil.c 1 14    14    88 190   210    0      1 7.5  4.1  280 0   0   -32 8.7   5.0   320   .62 0   0 5.4  3.0  280 0   0   -32 .64   .65   21    .12  0      - -
bitvector/s3_clnt_2_false-unreach-call_true-no-overflow.BV.c.cil.c 1 16    16    88 180   300    0      1 6.1  3.3  280 0   0   -32 8.5   4.8   310   .66 0   0 5.9  3.3  280 0   0   -32 .62   .62   21    .11  0      - -
bitvector/s3_clnt_3_false-unreach-call_true-no-overflow.BV.c.cil.c 1 4.6  4.6  60 73   150    0      1 5.6  3.0  270 0   0   -32 8.8   4.9   310   .66 0   0 6.2  3.5  270 0   0   -32 .62   .63   21    .11  0      - -
bitvector/s3_clnt_1_true-unreach-call_true-no-overflow.BV.c.cil.c 0 92    92    210 1100   430    0      - - - - 2 73    64    1000 0   0   2 46     26     750   .75 0  
bitvector/s3_clnt_2_true-unreach-call_true-no-overflow.BV.c.cil.c 0 35    35    160 550   360    .0041 - - - - 2 17    10    590 0   0   2 55     32     940   .68 0  
bitvector/s3_clnt_3_true-unreach-call_true-no-overflow.BV.c.cil.c 0 34    33    160 410   420    0      - - - - 2 14    8.2  550 0   0   2 34     19     860   .62 0  
bitvector/s3_srvr_1_alt_true-unreach-call_true-no-overflow.BV.c.cil.c 0 900    900    250 11000   460    0      - - - - 0 .60 .36 40 0   0   0 .023 .024 5.7 0    0  
bitvector/s3_srvr_1_true-unreach-call_true-no-overflow.BV.c.cil.c 0 900    900    370 11000   1500    .0041 - - - - 0 .64 .39 40 0   0   0 .020 .020 5.6 0    0  
bitvector/s3_srvr_2_alt_true-unreach-call_true-no-overflow_false-termination.BV.c.cil.c 0 900    900    350 12000   1400    .0041 - - - - 0 .62 .37 40 0   0   0 .020 .021 5.7 0    0  
bitvector/s3_srvr_2_true-unreach-call_true-no-overflow_false-termination.BV.c.cil.c 0 900    900    350 9600   1500    0      - - - - 0 .60 .36 41 0   0   0 .047 .049 5.5 0    0  
bitvector/s3_srvr_3_alt_true-unreach-call_true-no-overflow.BV.c.cil.c 0 900    900    420 12000   1000    0      - - - - 0 .67 .42 40 0   0   0 .020 .021 5.6 0    0  
bitvector/s3_srvr_3_true-unreach-call_true-no-overflow.BV.c.cil.c 0 900    900    430 11000   1100    0      - - - - 0 .61 .37 40 0   0   0 .021 .022 5.7 0    0  
bitvector/soft_float_1_true-unreach-call_true-no-overflow_true-termination.c.cil.c 0 1.4  1.1  66 16   31    0      - - - - 0 900    860    5100 0   0   2 140     120     770   .71 0  
bitvector/soft_float_2_true-unreach-call_true-no-overflow_true-termination.c.cil.c 0 1.2  .94 67 14   31    0      - - - - 0 830    770    7000 0   0   2 45     29     550   .66 0  
bitvector/soft_float_3_true-unreach-call_true-no-overflow_true-termination.c.cil.c 0 1.1  .81 66 13   31    0      - - - - 0 900    840    6700 0   0   0 960     890     800   .69 0  
bitvector/soft_float_4_true-unreach-call_true-no-overflow_true-termination.c.cil.c 0 4.3  4.1  65 67   31    0      - - - - 2 90    86    550 0   0   2 360     320     770   .71 0  
bitvector/soft_float_5_true-unreach-call_true-no-overflow_true-termination.c.cil.c 0 1.2  .97 67 15   31    0      - - - - 0 910    830    6800 0   0   2 30     17     600   .62 0  
bitvector-regression/implicitfloatconversion_false-unreach-call_true-termination.c 1 .14 .14 34 1.7 .85 0      1 4.2  2.3  250 0   0   1 12     7.1   310   .68 0   1 3.5  2.0  250 0   0   1 .56   .56   20    .041 .0082 - -
bitvector-regression/implicitunsignedconversion_false-unreach-call_true-termination.c 1 .15 .15 33 1.9 1.0  0      1 3.6  2.0  250 0   0   1 6.5   3.7   300   .66 0   1 3.8  2.2  240 0   0   1 .59   .59   20    .041 0      - -
bitvector-regression/integerpromotion_false-unreach-call_true-termination.c 1 .14 .14 34 1.9 1.0  0      1 3.8  2.1  250 0   0   1 13     7.3   310   .68 0   1 3.5  2.0  250 0   0   1 .56   .56   20    .041 0      - -
bitvector-regression/recHanoi03_false-unreach-call_true-termination.c 0 .84 .59 66 11   31    0      0 3.3  1.9  250 0   0   0 97     77     880   1.6  0   0 1.0  .65 50 0   0   0 .091  .090  11    0     .0041 - -
bitvector-regression/signextension2_false-unreach-call_true-termination.c 1 .14 .14 34 1.4 1.0  0      1 3.7  2.1  250 0   0   1 6.3   3.6   300   .66 0   1 3.5  2.1  250 0   0   1 .56   .56   20    .045 0      - -
bitvector-regression/signextension_false-unreach-call_true-termination.c 1 .13 .13 34 1.8 1.0  0      1 3.8  2.1  250 0   0   1 6.7   3.9   300   .66 0   1 3.5  2.1  250 0   0   1 .57   .57   20    .045 0      - -
bitvector-regression/implicitunsignedconversion_true-unreach-call_true-termination.c 0 .79 .54 66 8.2 31    0      - - - - 2 4.4  2.5  250 0   0   2 7.3   4.1   310   .62 0  
bitvector-regression/integerpromotion_true-unreach-call_true-termination.c 0 .80 .54 66 8.5 31    0      - - - - 2 4.2  2.4  250 0   0   2 13     7.6   300   .75 0  
bitvector-regression/signextension2_true-unreach-call_true-termination.c 0 .80 .54 66 11   31    0      - - - - 2 3.7  2.0  250 0   0   2 8.0   4.9   310   .66 0  
bitvector-regression/signextension_true-unreach-call_true-termination.c 0 .80 .54 68 9.6 31    0      - - - - 2 4.1  2.3  250 0   0   2 7.8   4.4   310   .62 0  
bitvector-loops/diamond_false-unreach-call2.i 1 .38 .37 35 5.2 31    0      1 4.6  2.5  250 0   0   1 8.4   4.8   320   .66 0   1 3.9  2.2  260 0   0   1 .58   .58   20    .049 .0041 - -
bitvector-loops/overflow_false-unreach-call1.i 0 36    36    43 470   3000    .053  0 .62 .38 41 0   0   0 .023 .024 5.6 0    0   0 .92 .59 47 0   0   0 .0015 .0020 .41 0     0      - -
bitvector-loops/verisec_sendmail__tTflag_arr_one_loop_false-unreach-call_true-termination.i 1 3.5  3.4  38 47   330    .0041 1 5.4  3.1  290 0   0   0 98     66     6900   1.4  0   0 4.0  2.3  250 0   0   1 .59   .59   21    .049 0      - -
sv-benchmarks/c/ status score witness inspect witness cpu (s) wall (s) mem (MB) energy (J) blkio-w (MB) blkio-r (MB) status score witness inspect witness cpu (s) wall (s) mem (MB) energy blkio-w (MB) blkio-r (MB) status score witness inspect witness cpu (s) wall (s) mem (MB) energy blkio-w (MB) blkio-r (MB) status score witness inspect witness cpu (s) wall (s) mem (MB) energy blkio-w (MB) blkio-r (MB) status score witness inspect witness cpu (s) wall (s) mem (MB) energy blkio-w (MB) blkio-r (MB) status score witness inspect witness cpu (s) wall (s) mem (MB) energy blkio-w (MB) blkio-r (MB) status score witness inspect witness cpu (s) wall (s) mem (MB) energy blkio-w (MB) blkio-r (MB)
total 50 11 11000 11000 6400 130000 33000 .20   14 11 59 33 3200 0   0   14 -89 320 220 11000 9.5 0   14 7 50 29 3000 0   0   14 -88 6.6 6.6 240 .72 .016 36 38 4100 3800 34000 0   0   36 30 8700 8300 21000 16 0  
    correct results 11 11 40 40 510 520 1100 .0041 11 11 54 30 2900 0   0   7 7 100 59 2500 4.7 0   7 7 26 15 1700 0   0   8 8 4.6 4.6 160 .37 .012 19 38 580 510 8000 0   0   15 30 1000 840 8600 10 0  
        correct true 0 0 0 0 0 19 38 580 510 8000 0   0   15 30 1000 840 8600 10 0  
        correct false 11 11 40 40 510 520 1100 .0041 11 11 54 30 2900 0   0   7 7 100 59 2500 4.7 0   7 7 26 15 1700 0   0   8 8 4.6 4.6 160 .37 .012 0 0
    incorrect results 0 0 3 -96 26 15 950 1.9 0   0 3 -96 1.9 1.9 62 .35 0     0 0
        incorrect true 0 0 3 -96 26 15 950 1.9 0   0 3 -96 1.9 1.9 62 .35 0     0 0
        incorrect false 0 0 0 0 0 0 0
score (50 tasks, max score: 86) 11 11 -89 7 -88 38 30
Run set depthk.sv-comp19_prop-reachsafety.ReachSafety-BitVectors cpa-seq-validate-violation-witnesses-depthk.sv-comp19_prop-reachsafety.ReachSafety-BitVectors uautomizer-validate-violation-witnesses-depthk.sv-comp19_prop-reachsafety.ReachSafety-BitVectors cpa-witness2test-validate-violation-witnesses-depthk.sv-comp19_prop-reachsafety.ReachSafety-BitVectors fshell-witness2test-validate-violation-witnesses-depthk.sv-comp19_prop-reachsafety.ReachSafety-BitVectors cpa-seq-validate-correctness-witnesses-depthk.sv-comp19_prop-reachsafety.ReachSafety-BitVectors uautomizer-validate-correctness-witnesses-depthk.sv-comp19_prop-reachsafety.ReachSafety-BitVectors