Tool CPAchecker 1.7-svn 29852 ULTIMATE Automizer 0.1.23-635dfa2a CPA-witness2test 1.7-svn 29852 CProver witness2test 0.1 CPAchecker 1.7-svn 29852 ULTIMATE Automizer 0.1.23-635dfa2a
Limits timelimit: 900 s, memlimit: 15000 MB, CPU core limit: 8 timelimit: 90 s, memlimit: 7000 MB, CPU core limit: 2 timelimit: 900 s, memlimit: 7000 MB, CPU core limit: 2
Host apollon*
OS Linux 4.15.0-42-generic
System CPU: Intel Xeon E3-1230 v5 @ 3.40 GHz, cores: 8, frequency: 3.8 GHz, Turbo Boost: disabled; RAM: 33546 MB
Date of execution 2018-12-05 05:46:16 CET 2018-12-06 09:44:44 CET 2018-12-06 10:50:29 CET 2018-12-06 10:57:45 CET 2018-12-12 19:32:16 CET 2018-12-06 08:37:23 CET 2018-12-06 09:52:34 CET
Run set cpa-seq.sv-comp19_prop-reachsafety.ReachSafety-Heap cpa-seq-validate-violation-witnesses-cpa-seq.sv-comp19_prop-reachsafety.ReachSafety-Heap uautomizer-validate-violation-witnesses-cpa-seq.sv-comp19_prop-reachsafety.ReachSafety-Heap cpa-witness2test-validate-violation-witnesses-cpa-seq.sv-comp19_prop-reachsafety.ReachSafety-Heap fshell-witness2test-validate-violation-witnesses-cpa-seq.sv-comp19_prop-reachsafety.ReachSafety-Heap cpa-seq-validate-correctness-witnesses-cpa-seq.sv-comp19_prop-reachsafety.ReachSafety-Heap uautomizer-validate-correctness-witnesses-cpa-seq.sv-comp19_prop-reachsafety.ReachSafety-Heap
Options -svcomp19 -heap 10000M -benchmark -timelimit 900s -witnessValidation -setprop witness.checkProgramHash=false -heap 5000m -benchmark -setprop cpa.predicate.memoryAllocationsAlwaysSucceed=true -setprop cpa.smg.memoryAllocationFunctions=malloc,__kmalloc,kmalloc,kzalloc,kzalloc_node,ldv_zalloc,ldv_malloc -setprop cpa.smg.arrayAllocationFunctions=calloc,kmalloc_array,kcalloc -setprop cpa.smg.zeroingMemoryAllocation=calloc,kzalloc,kcalloc,kzalloc_node,ldv_zalloc -setprop cpa.smg.deallocationFunctions=free,kfree,kfree_const -witness ../../results-verified/cpa-seq.2018-12-05_0546.logfiles/${rundefinition_name}.${inputfile_name}.files/witness.graphml --full-output --validate ../../results-verified/cpa-seq.2018-12-05_0546.logfiles/${rundefinition_name}.${inputfile_name}.files/witness.graphml -setprop witness.checkProgramHash=false -heap 5000m -benchmark -setprop analysis.summaryEdges=true -setprop cpa.callstack.skipVoidRecursion=true -setprop cpa.callstack.skipFunctionPointerRecursion=true -witness ../../results-verified/cpa-seq.2018-12-05_0546.logfiles/${rundefinition_name}.${inputfile_name}.files/witness.graphml --graphml-witness ../../results-verified/cpa-seq.2018-12-05_0546.logfiles/${rundefinition_name}.${inputfile_name}.files/witness.graphml -witnessValidation -setprop witness.checkProgramHash=false -heap 5000m -benchmark -setprop cpa.predicate.memoryAllocationsAlwaysSucceed=true -witness ../../results-verified/cpa-seq.2018-12-05_0546.logfiles/${rundefinition_name}.${inputfile_name}.files/witness.graphml --full-output --validate ../../results-verified/cpa-seq.2018-12-05_0546.logfiles/${rundefinition_name}.${inputfile_name}.files/witness.graphml
sv-benchmarks/c/ status score witness inspect witness cpu (s) wall (s) mem (MB) energy (J) blkio-w (MB) blkio-r (MB) status score witness inspect witness cpu (s) wall (s) mem (MB) energy blkio-w (MB) blkio-r (MB) status score witness inspect witness cpu (s) wall (s) mem (MB) energy blkio-w (MB) blkio-r (MB) status score witness inspect witness cpu (s) wall (s) mem (MB) energy blkio-w (MB) blkio-r (MB) status score witness inspect witness cpu (s) wall (s) mem (MB) energy blkio-w (MB) blkio-r (MB) status score witness inspect witness cpu (s) wall (s) mem (MB) energy blkio-w (MB) blkio-r (MB) status score witness inspect witness cpu (s) wall (s) mem (MB) energy blkio-w (MB) blkio-r (MB)
heap-manipulation/bubble_sort_linux_false-unreach-call_false-valid-memcleanup.i timeout 0 wit inspect 900   880   2300 7400 .016  0     timeout 0 wit inspect 92    82    810 0     0   timeout 0 --- inspect 96     77     830   .62 0     unknown 0 --- inspect 1.1 .69 50 0   0     error (1) 0 --- inspect .078  .078  11    0     .037  - --- inspect - --- inspect
heap-manipulation/dll_of_dll_false-unreach-call_false-valid-memcleanup.i assertion 0 --- inspect 42   22   2200 410 .025  0     error (invalid witness file) 0 --- inspect .62 .37 41 0     0   error (2) 0 --- inspect .020 .023 5.6 0    0     error (invalid witness file) 0 --- inspect 1.0 .65 49 0   0     error (invalid witness file) 0 --- inspect .0060 .0078 .53 0     0      - --- inspect - --- inspect
heap-manipulation/merge_sort_false-unreach-call_false-valid-memcleanup.i false(unreach-call) 0 wit inspect 52   22   2100 420 .41   0     true -32 wit inspect 5.6  3.1  250 0     0   error (7) 0 --- inspect 18     10     310   .68 0     unknown 0 --- inspect 4.5 2.6  250 0   0     true -32 --- inspect .63   .63   21    .082 0      - --- inspect - --- inspect
heap-manipulation/sll_to_dll_rev_false-unreach-call_false-valid-memcleanup.i false(unreach-call) 0 wit inspect 8.9 2.7 490 70 .13   0     true -32 wit inspect 5.2  2.8  260 0     0   error (7) 0 --- inspect 21     12     320   .68 0     unknown 0 --- inspect 4.4 2.6  250 0   0     true -32 --- inspect .63   .63   21    .082 0      - --- inspect - --- inspect
heap-manipulation/tree_false-unreach-call_false-valid-deref.i false(unreach-call) 1 wit inspect 14   3.6 550 110 .090  0     false(unreach-call) 1 wit inspect 5.4  2.9  280 0     0   error (7) 0 --- inspect 16     9.4   310   .68 0     unknown 0 --- inspect 5.1 2.9  250 0   .11  false(unreach-call) 1 --- inspect .63   .63   21    .074 .025  - --- inspect - --- inspect
heap-manipulation/tree_false-unreach-call_false-valid-memcleanup.i false(unreach-call) 1 wit inspect 15   3.8 550 110 .041  0     false(unreach-call) 1 wit inspect 6.1  3.3  260 0     0   error (7) 0 --- inspect 17     10     320   .71 0     unknown 0 --- inspect 4.7 2.7  260 0   .11  false(unreach-call) 1 --- inspect .63   .63   21    .074 0      - --- inspect - --- inspect
heap-manipulation/bubble_sort_linux_true-unreach-call_true-valid-memsafety.i timeout 0 wit inspect 900   880   1800 7300 .016  0     - --- inspect - --- inspect - --- inspect - --- inspect timeout 0 wit inspect 900    880    1600 0   0   timeout 0 --- inspect 960     930     1200   .75 0  
heap-manipulation/dancing_true-unreach-call_false-valid-memtrack.i error (recursion) 0 --- inspect 7.1 2.7 370 63 0      0     - --- inspect - --- inspect - --- inspect - --- inspect error (invalid witness file) 0 --- inspect .75 .47 41 0   0   error (2) 0 --- inspect .022 .022 5.6 0    0  
heap-manipulation/dll_of_dll_true-unreach-call_true-valid-memsafety.i assertion 0 --- inspect 44   22   2200 400 .025  0     - --- inspect - --- inspect - --- inspect - --- inspect error (invalid witness file) 0 --- inspect .59 .36 42 0   0   error (2) 0 --- inspect .022 .023 5.6 0    0  
heap-manipulation/merge_sort_true-unreach-call_true-valid-memsafety.i timeout 0 wit inspect 910   730   8200 7500 .016  0     - --- inspect - --- inspect - --- inspect - --- inspect timeout 0 wit inspect 900    840    7000 0   0   timeout 0 --- inspect 960     900     2600   .78 0  
heap-manipulation/sll_to_dll_rev_true-unreach-call_true-valid-memsafety.i timeout 0 wit inspect 920   880   6500 7600 .025  0     - --- inspect - --- inspect - --- inspect - --- inspect unknown 0 wit inspect 100    89    990 0   0   timeout 0 --- inspect 960     950     770   1.7  0  
heap-manipulation/tree_true-unreach-call.i timeout 0 wit inspect 900   880   3900 6300 .025  0     - --- inspect - --- inspect - --- inspect - --- inspect timeout 0 wit inspect 900    880    2900 0   0   true 2 --- inspect 22     14     580   .66 0  
list-properties/alternating_list_false-unreach-call_false-valid-memcleanup.i false(unreach-call) 0 wit inspect 9.7 2.9 490 73 .053  0     true -32 wit inspect 4.9  2.7  250 0     0   true -32 --- inspect 20     12     510   .62 0     unknown 0 --- inspect 4.2 2.4  250 0   0     true -32 --- inspect .62   .63   20    .066 0      - --- inspect - --- inspect
list-properties/list_false-unreach-call_false-valid-memcleanup.i false(unreach-call) 0 wit inspect 11   3.1 510 89 .19   0     unknown 0 wit inspect 5.2  2.9  260 0     0   true -32 --- inspect 21     13     610   .62 0     unknown 0 --- inspect 4.2 2.4  250 0   0     true -32 --- inspect .65   .65   21    .066 0      - --- inspect - --- inspect
list-properties/list_flag_false-unreach-call_false-valid-memcleanup.i false(unreach-call) 1 wit inspect 8.3 2.5 460 65 .045  0     true -32 wit inspect 4.9  2.7  250 0     0   true -32 --- inspect 14     8.5   540   .62 0     unknown 0 --- inspect 4.0 2.4  250 0   0     false(unreach-call) 1 --- inspect .62   .62   20    .066 0      - --- inspect - --- inspect
list-properties/list_search_false-unreach-call_false-valid-memcleanup.i false(unreach-call) 1 wit inspect 9.9 2.9 500 85 .049  0     false(unreach-call) 1 wit inspect 5.8  3.2  270 0     0   timeout (false(unreach-call)) 0 --- inspect 92     81     700   .62 0     unknown 0 --- inspect 4.7 2.7  260 0   0     false(unreach-call) 1 --- inspect .64   .64   21    .070 .025  - --- inspect - --- inspect
list-properties/simple_false-unreach-call_false-valid-memcleanup.i false(unreach-call) 0 wit inspect 8.2 2.5 440 63 .049  0     unknown 0 wit inspect 5.3  2.9  250 0     0   true -32 --- inspect 18     12     480   .62 0     unknown 0 --- inspect 4.3 2.5  250 0   0     true -32 --- inspect .62   .62   20    .066 0      - --- inspect - --- inspect
list-properties/splice_false-unreach-call_false-valid-memcleanup.i false(unreach-call) 0 wit inspect 11   3.1 390 87 .082  0     true -32 wit inspect 4.9  2.6  260 0     0   timeout 0 --- inspect 97     76     980   .66 0     unknown 0 --- inspect 4.2 2.4  250 0   0     true -32 --- inspect .65   .66   21    .070 0      - --- inspect - --- inspect
list-properties/alternating_list_true-unreach-call_true-valid-memsafety.i timeout 0 wit inspect 900   880   3300 8400 .016  0     - --- inspect - --- inspect - --- inspect - --- inspect timeout 0 wit inspect 900    880    3000 0   0   timeout 0 --- inspect 960     920     1000   .64 0  
list-properties/list_flag_true-unreach-call_false-valid-memtrack.i timeout 0 wit inspect 900   890   2200 6800 .016  0     - --- inspect - --- inspect - --- inspect - --- inspect timeout 0 wit inspect 900    890    2900 0   0   timeout 0 --- inspect 960     880     1100   .65 0  
list-properties/list_search_true-unreach-call_false-valid-memcleanup.i true 2 wit inspect 19   6.0 680 180 .025  0     - --- inspect - --- inspect - --- inspect - --- inspect true 2 wit inspect 23    14    650 0   0   true 2 --- inspect 120     100     770   .62 0  
list-properties/list_true-unreach-call_false-valid-memtrack.i timeout 0 wit inspect 910   880   3500 6700 .016  0     - --- inspect - --- inspect - --- inspect - --- inspect timeout 0 wit inspect 900    880    3900 0   0   timeout 0 --- inspect 960     930     960   .64 0  
list-properties/simple_built_from_end_true-unreach-call_false-valid-memtrack.i timeout 0 wit inspect 900   890   2200 6000 .016  0     - --- inspect - --- inspect - --- inspect - --- inspect timeout 0 wit inspect 900    890    1900 0   0   timeout 0 --- inspect 960     930     1700   .63 0  
list-properties/simple_true-unreach-call_false-valid-memtrack.i timeout 0 wit inspect 900   890   2000 6200 .016  0     - --- inspect - --- inspect - --- inspect - --- inspect timeout 0 wit inspect 900    890    2000 0   0   timeout 0 --- inspect 960     930     1200   1.0  0  
list-properties/splice_true-unreach-call_false-valid-memtrack.i timeout 0 wit inspect 920   890   3800 6600 .025  0     - --- inspect - --- inspect - --- inspect - --- inspect timeout 0 wit inspect 900    880    4400 0   0   timeout 0 --- inspect 960     910     1400   1.2  0  
ldv-regression/1_3_true-termination.c_false-unreach-call.i false(unreach-call) 1 wit inspect 3.1 1.4 260 26 .0082 0     false(unreach-call) 1 wit inspect 3.9  2.2  250 0     0   false(unreach-call) 1 --- inspect 7.2   4.5   300   .62 0     false(unreach-call) 1 --- inspect 3.8 2.3  250 0   .11  false(unreach-call) 1 --- inspect .58   .58   20    .057 0      - --- inspect - --- inspect
ldv-regression/alt_test_true-termination.c_false-unreach-call.i false(unreach-call) 1 wit inspect 4.3 1.7 290 40 0      0     false(unreach-call) 1 wit inspect 4.9  2.7  250 0     0   false(unreach-call) 1 --- inspect 10     6.1   340   .66 0     unknown 0 --- inspect 4.7 2.6  250 0   .11  false(unreach-call) 1 --- inspect .68   .67   20    .086 0      - --- inspect - --- inspect
ldv-regression/callfpointer_true-termination.c_false-unreach-call.i false(unreach-call) 1 wit inspect 2.8 1.3 250 28 0      0     false(unreach-call) 1 wit inspect 3.8  2.1  250 0     0   false(unreach-call) 1 --- inspect 7.0   4.0   310   .66 0     false(unreach-call) 1 --- inspect 3.5 2.1  250 0   0     false(unreach-call) 1 --- inspect .57   .57   20    .045 0      - --- inspect - --- inspect
ldv-regression/fo_test_true-termination.c_false-unreach-call.i false(unreach-call) 1 wit inspect 3.9 1.6 290 39 0      0     false(unreach-call) 1 wit inspect 4.7  2.6  260 0     0   unknown 0 --- inspect 16     9.3   320   .75 0     unknown 0 --- inspect 4.4 2.6  250 0   .30  false(unreach-call) 1 --- inspect .63   .63   20    .074 0      - --- inspect - --- inspect
ldv-regression/mutex_lock_int_true-termination.c_false-unreach-call.i false(unreach-call) 1 wit inspect 3.1 1.4 260 25 .0082 0     false(unreach-call) 1 wit inspect 4.4  2.5  250 0     0   false(unreach-call) 1 --- inspect 7.3   4.1   310   .66 0     false(unreach-call) 1 --- inspect 3.7 2.1  240 0   0     false(unreach-call) 1 --- inspect .58   .58   20    .049 0      - --- inspect - --- inspect
ldv-regression/mutex_lock_struct_true-termination.c_false-unreach-call.i false(unreach-call) 1 wit inspect 3.0 1.3 260 27 .0082 0     false(unreach-call) 1 wit inspect 3.8  2.1  250 0     0   false(unreach-call) 1 --- inspect 8.2   4.5   310   .66 0     false(unreach-call) 1 --- inspect 3.6 2.1  250 0   0     false(unreach-call) 1 --- inspect .57   .57   20    .045 0      - --- inspect - --- inspect
ldv-regression/recursive_list_true-termination.c_false-unreach-call.i false(unreach-call) 1 wit inspect 3.1 1.4 270 30 0      0     false(unreach-call) 1 wit inspect 4.5  2.5  250 0     0   false(unreach-call) 1 --- inspect 7.7   4.8   310   .66 0     false(unreach-call) 1 --- inspect 3.7 2.1  250 0   0     false(unreach-call) 1 --- inspect .56   .56   20    .049 .0041 - --- inspect - --- inspect
ldv-regression/rule57_ebda_blast_true-termination.c_false-unreach-call.i false(unreach-call) 1 wit inspect 3.2 1.4 260 34 0      0     false(unreach-call) 1 wit inspect 5.0  2.8  260 0     0   false(unreach-call) 1 --- inspect 8.3   4.8   310   .62 0     unknown 0 --- inspect 4.0 2.3  240 0   .11  false(unreach-call) 1 --- inspect .62   .61   21    .066 0      - --- inspect - --- inspect
ldv-regression/rule60_list2_true-termination.c_false-unreach-call_1.i false(unreach-call) 1 wit inspect 4.0 1.6 300 34 0      0     false(unreach-call) 1 wit inspect 5.3  2.9  270 0     0   false(unreach-call) 1 --- inspect 13     8.1   490   .66 0     exception 0 --- inspect 4.4 2.5  260 0   0     false(unreach-call) 1 --- inspect .64   .63   21    .078 0      - --- inspect - --- inspect
ldv-regression/stateful_check_false-unreach-call_false-termination.i false(unreach-call) 1 wit inspect 4.6 1.8 290 38 .025  0     false(unreach-call) 1 wit inspect 5.0  2.7  250 0     0   false(unreach-call) 1 --- inspect 8.2   4.9   310   .62 0     unknown 0 --- inspect 4.1 2.4  250 0   0     true -32 --- inspect .59   .59   21    .057 .0041 - --- inspect - --- inspect
ldv-regression/test_while_int_true-termination.c_false-unreach-call.i false(unreach-call) 1 wit inspect 3.6 1.6 260 34 .012  0     false(unreach-call) 1 wit inspect 5.2  2.8  250 0     0   false(unreach-call) 1 --- inspect 7.2   4.1   300   .66 0     false(unreach-call) 1 --- inspect 3.8 2.2  250 0   0     false(unreach-call) 1 --- inspect .58   .58   21    .045 0      - --- inspect - --- inspect
ldv-regression/test_while_int_true-termination.c_false-unreach-call_1.i false(unreach-call) 1 wit inspect 3.6 1.5 270 33 .012  0     false(unreach-call) 1 wit inspect 4.6  2.5  250 0     0   false(unreach-call) 1 --- inspect 7.8   4.7   300   .66 0     false(unreach-call) 1 --- inspect 3.6 2.1  250 0   0     false(unreach-call) 1 --- inspect .57   .57   20    .045 0      - --- inspect - --- inspect
ldv-regression/alias_of_return_2_true-termination.c_true-unreach-call.i true 2 wit inspect 2.9 1.3 260 30 0      0     - --- inspect - --- inspect - --- inspect - --- inspect true 2 wit inspect 4.7  2.6  250 0   0   true 2 --- inspect 8.6   4.9   310   .66 0  
ldv-regression/alias_of_return_2_true-termination.c_true-unreach-call_1.i true 2 wit inspect 2.8 1.3 250 26 0      0     - --- inspect - --- inspect - --- inspect - --- inspect true 2 wit inspect 3.5  2.0  250 0   0   true 2 --- inspect 9.2   5.4   310   .66 0  
ldv-regression/alias_of_return_true-termination.c_true-unreach-call.i true 2 wit inspect 3.0 1.3 250 27 0      0     - --- inspect - --- inspect - --- inspect - --- inspect true 2 wit inspect 3.6  2.0  250 0   0   true 2 --- inspect 7.5   4.3   310   .66 0  
ldv-regression/alias_of_return_true-termination.c_true-unreach-call_1.i true 2 wit inspect 2.9 1.3 250 26 0      0     - --- inspect - --- inspect - --- inspect - --- inspect true 2 wit inspect 3.7  2.1  250 0   0   true 2 --- inspect 7.7   4.7   310   .66 0  
ldv-regression/ex3_forlist_true-termination.c_true-unreach-call.i true 2 wit inspect 2.9 1.3 250 31 0      0     - --- inspect - --- inspect - --- inspect - --- inspect true 2 wit inspect 21    14    510 0   0   true 2 --- inspect 36     24     600   .66 0  
ldv-regression/just_assert_true-termination.c_true-unreach-call.i true 2 wit inspect 2.7 1.2 260 25 0      0     - --- inspect - --- inspect - --- inspect - --- inspect true 2 wit inspect 3.3  1.9  250 0   0   true 2 --- inspect 7.6   4.6   310   .66 0  
ldv-regression/mutex_lock_int_true-termination.c_true-unreach-call_1.i true 2 wit inspect 3.0 1.3 250 25 0      0     - --- inspect - --- inspect - --- inspect - --- inspect true 2 wit inspect 3.6  2.0  250 0   0   true 2 --- inspect 9.5   5.7   320   .66 0  
ldv-regression/mutex_lock_struct_true-termination.c_true-unreach-call_1.i true 2 wit inspect 2.9 1.3 250 29 0      0     - --- inspect - --- inspect - --- inspect - --- inspect true 2 wit inspect 4.4  2.5  250 0   0   true 2 --- inspect 9.3   5.2   310   .66 0  
ldv-regression/nested_structure_noptr_true-termination.c_true-unreach-call.i true 2 wit inspect 2.9 1.3 260 29 0      0     - --- inspect - --- inspect - --- inspect - --- inspect true 2 wit inspect 3.3  1.9  250 0   0   true 2 --- inspect 7.6   4.2   320   .66 0  
ldv-regression/nested_structure_noptr_true-unreach-call_true-termination.i true 2 wit inspect 2.9 1.3 260 26 0      0     - --- inspect - --- inspect - --- inspect - --- inspect true 2 wit inspect 3.7  2.1  250 0   0   true 2 --- inspect 8.9   4.9   320   .66 0  
ldv-regression/nested_structure_ptr_true-termination.c_true-unreach-call.i true 2 wit inspect 2.9 1.3 260 26 0      0     - --- inspect - --- inspect - --- inspect - --- inspect true 2 wit inspect 3.7  2.1  250 0   0   true 2 --- inspect 7.3   4.2   300   .66 0  
ldv-regression/nested_structure_ptr_true-unreach-call_true-termination.i true 2 wit inspect 3.0 1.3 250 26 0      0     - --- inspect - --- inspect - --- inspect - --- inspect true 2 wit inspect 4.7  2.6  250 0   0   true 2 --- inspect 8.6   4.9   310   .66 0  
ldv-regression/nested_structure_true-termination.c_true-unreach-call.i true 2 wit inspect 2.9 1.3 260 26 0      0     - --- inspect - --- inspect - --- inspect - --- inspect true 2 wit inspect 3.5  2.0  250 0   0   true 2 --- inspect 9.1   5.1   310   .66 0  
ldv-regression/nested_structure_true-unreach-call_true-termination.i true 2 wit inspect 3.0 1.3 260 28 0      0     - --- inspect - --- inspect - --- inspect - --- inspect true 2 wit inspect 4.0  2.2  250 0   0   true 2 --- inspect 8.0   4.5   310   .66 0  
ldv-regression/oomInt_true-termination.c_true-unreach-call.i true 2 wit inspect 2.8 1.3 260 28 0      0     - --- inspect - --- inspect - --- inspect - --- inspect true 2 wit inspect 4.0  2.2  250 0   0   true 2 --- inspect 7.8   4.5   310   .66 0  
ldv-regression/oomInt_true-termination.c_true-unreach-call_1.i true 2 wit inspect 2.9 1.3 250 25 0      0     - --- inspect - --- inspect - --- inspect - --- inspect true 2 wit inspect 3.6  2.0  250 0   0   true 2 --- inspect 9.0   5.3   310   .66 0  
ldv-regression/rule57_ebda_blast_true-termination.c_true-unreach-call_1.i true 2 wit inspect 3.4 1.4 280 29 0      0     - --- inspect - --- inspect - --- inspect - --- inspect true 2 wit inspect 4.3  2.4  260 0   0   true 2 --- inspect 9.8   5.5   330   .66 0  
ldv-regression/rule60_list2_true-termination.c_true-unreach-call.i true 2 wit inspect 4.0 1.6 290 35 0      0     - --- inspect - --- inspect - --- inspect - --- inspect true 2 wit inspect 4.3  2.3  260 0   0   true 2 --- inspect 22     14     510   .62 0  
ldv-regression/rule60_list_true-termination.c_true-unreach-call.i true 2 wit inspect 3.8 1.5 290 37 0      0     - --- inspect - --- inspect - --- inspect - --- inspect true 2 wit inspect 4.1  2.3  260 0   0   true 2 --- inspect 11     6.6   380   .66 0  
ldv-regression/sizeofparameters_test_true-termination.c_true-unreach-call.i true 2 wit inspect 3.6 1.5 280 34 0      0     - --- inspect - --- inspect - --- inspect - --- inspect true 2 wit inspect 3.9  2.2  250 0   0   true 2 --- inspect 7.8   4.3   310   .66 0  
ldv-regression/structure_assignment_true-termination.c_true-unreach-call.i true 2 wit inspect 2.8 1.3 260 29 0      0     - --- inspect - --- inspect - --- inspect - --- inspect true 2 wit inspect 4.3  2.5  250 0   0   true 2 --- inspect 7.2   4.5   310   .66 0  
ldv-regression/test_address_true-termination.c_true-unreach-call.i true 2 wit inspect 3.6 1.5 280 37 0      0     - --- inspect - --- inspect - --- inspect - --- inspect true 2 wit inspect 5.2  2.9  250 0   0   true 2 --- inspect 8.6   4.8   320   .66 0  
ldv-regression/test_cut_trace_true-termination.c_true-unreach-call.i true 2 wit inspect 2.8 1.3 250 29 0      0     - --- inspect - --- inspect - --- inspect - --- inspect true 2 wit inspect 3.3  1.9  250 0   0   true 2 --- inspect 7.8   4.8   310   .62 0  
ldv-regression/test_malloc-1_true-unreach-call_true-termination.i true 2 wit inspect 3.7 1.5 290 34 0      0     - --- inspect - --- inspect - --- inspect - --- inspect true 2 wit inspect 4.2  2.3  260 0   0   true 2 --- inspect 8.2   4.6   310   .66 0  
ldv-regression/test_malloc-2_true-unreach-call_true-termination.i true 2 wit inspect 3.8 1.5 280 31 0      0     - --- inspect - --- inspect - --- inspect - --- inspect true 2 wit inspect 4.5  2.4  280 0   0   true 2 --- inspect 9.5   5.6   320   .66 0  
ldv-regression/test_overflow_true-termination.c_true-unreach-call.i true 2 wit inspect 4.0 1.5 280 36 0      0     - --- inspect - --- inspect - --- inspect - --- inspect true 2 wit inspect 5.8  3.1  280 0   0   true 2 --- inspect 10     5.8   310   .66 0  
ldv-regression/test_union_cast-1_true-unreach-call_true-termination.i true 2 wit inspect 2.9 1.3 260 26 0      0     - --- inspect - --- inspect - --- inspect - --- inspect true 2 wit inspect 3.8  2.1  250 0   0   true 2 --- inspect 8.1   4.6   300   .66 0  
ldv-regression/test_union_cast-2_true-unreach-call_true-termination.i true 2 wit inspect 2.9 1.3 260 28 0      0     - --- inspect - --- inspect - --- inspect - --- inspect true 2 wit inspect 3.7  2.0  250 0   0   true 2 --- inspect 7.6   4.3   310   .66 0  
ldv-regression/test_union_cast_true-termination.c_true-unreach-call.i true 2 wit inspect 3.0 1.3 250 29 0      0     - --- inspect - --- inspect - --- inspect - --- inspect true 2 wit inspect 3.8  2.2  240 0   0   true 2 --- inspect 7.1   4.0   310   .66 0  
ldv-regression/test_union_cast_true-termination.c_true-unreach-call_1.i true 2 wit inspect 2.9 1.3 250 25 0      0     - --- inspect - --- inspect - --- inspect - --- inspect true 2 wit inspect 3.6  2.1  250 0   0   true 2 --- inspect 7.3   4.1   300   .66 0  
ldv-regression/test_union_true-termination.c_true-unreach-call.i true 2 wit inspect 2.8 1.3 250 26 0      0     - --- inspect - --- inspect - --- inspect - --- inspect true 2 wit inspect 4.9  2.7  250 0   0   true 2 --- inspect 8.1   4.5   310   .66 0  
ldv-regression/test_union_true-termination.c_true-unreach-call_1.i true 2 wit inspect 2.8 1.3 250 27 0      0     - --- inspect - --- inspect - --- inspect - --- inspect true 2 wit inspect 3.6  2.1  250 0   0   true 2 --- inspect 7.0   4.4   310   .66 0  
ldv-regression/volatile_alias_true-termination.c_true-unreach-call.i true 2 wit inspect 3.0 1.3 250 32 0      0     - --- inspect - --- inspect - --- inspect - --- inspect true 2 wit inspect 3.3  1.9  250 0   0   true 2 --- inspect 7.4   4.1   310   .62 0  
ldv-regression/volatile_alias_true-termination.c_true-unreach-call_1.i true 2 wit inspect 2.9 1.3 260 28 0      0     - --- inspect - --- inspect - --- inspect - --- inspect true 2 wit inspect 4.6  2.5  250 0   0   true 2 --- inspect 7.3   4.5   310   .66 0  
ldv-regression/test02_false-unreach-call_true-termination.c false(unreach-call) 1 wit inspect 2.9 1.3 260 28 0      0     false(unreach-call) 1 wit inspect 4.2  2.3  250 0     0   false(unreach-call) 1 --- inspect 7.4   4.6   310   .66 0     false(unreach-call) 1 --- inspect 3.5 2.1  240 0   0     false(unreach-call) 1 --- inspect .61   .61   20    .045 0      - --- inspect - --- inspect
ldv-regression/test06_false-unreach-call_true-termination.c false(unreach-call) 1 wit inspect 3.1 1.4 260 33 0      0     false(unreach-call) 1 wit inspect 4.2  2.3  250 0     0   false(unreach-call) 1 --- inspect 7.5   4.2   320   .62 0     false(unreach-call) 1 --- inspect 3.8 2.2  250 0   0     false(unreach-call) 1 --- inspect .59   .59   20    .057 0      - --- inspect - --- inspect
ldv-regression/test08_false-unreach-call_true-termination.c false(unreach-call) 1 wit inspect 3.0 1.4 260 28 0      0     false(unreach-call) 1 wit inspect 4.6  2.6  250 0     0   false(unreach-call) 1 --- inspect 7.1   4.1   300   .62 0     false(unreach-call) 1 --- inspect 3.8 2.2  250 0   0     false(unreach-call) 1 --- inspect .56   .56   20    .045 0      - --- inspect - --- inspect
ldv-regression/test12_false-unreach-call_true-termination.c false(unreach-call) 1 wit inspect 2.9 1.3 260 27 0      0     false(unreach-call) 1 wit inspect 3.9  2.1  250 0     0   false(unreach-call) 1 --- inspect 7.0   4.4   310   .62 0     false(unreach-call) 1 --- inspect 3.5 2.0  240 0   0     false(unreach-call) 1 --- inspect .59   .62   20    .045 0      - --- inspect - --- inspect
ldv-regression/test21_false-unreach-call_true-termination.c false(unreach-call) 1 wit inspect 3.0 1.4 270 32 0      0     false(unreach-call) 1 wit inspect 4.2  2.3  260 0     0   false(unreach-call) 1 --- inspect 9.6   5.6   310   .66 0     false(unreach-call) 1 --- inspect 3.8 2.2  250 0   0     false(unreach-call) 1 --- inspect .58   .58   20    .057 0      - --- inspect - --- inspect
ldv-regression/test22_false-unreach-call.c false(unreach-call) 1 wit inspect 5.1 1.9 310 45 .037  0     false(unreach-call) 1 wit inspect 4.2  2.4  260 0     0   false(unreach-call) 1 --- inspect 11     6.6   400   .62 0     unknown 0 --- inspect 4.0 2.3  250 0   0     true -32 --- inspect 2.2    2.2    21    .057 0      - --- inspect - --- inspect
ldv-regression/test23_false-unreach-call.c false(unreach-call) 1 wit inspect 8.3 2.9 470 75 .037  0     false(unreach-call) 1 wit inspect 5.2  2.9  270 0     0   out of memory 0 --- inspect 90     59     7000   .84 .033 unknown 0 --- inspect 4.3 2.5  250 0   0     true -32 --- inspect .60   .60   20    .057 0      - --- inspect - --- inspect
ldv-regression/test24_false-unreach-call.c false(unreach-call) 1 wit inspect 4.7 1.9 290 41 .029  0     false(unreach-call) 1 wit inspect 5.9  3.4  280 0     0   out of memory 0 --- inspect 85     53     7000   1.6  0     unknown 0 --- inspect 4.1 2.4  250 0   0     true -32 --- inspect .59   .59   21    .057 0      - --- inspect - --- inspect
ldv-regression/test25_false-unreach-call_true-termination.c false(unreach-call) 1 wit inspect 13   4.6 600 120 .28   0     false(unreach-call) 1 wit inspect 5.7  3.2  280 0     0   false(unreach-call) 1 --- inspect 30     18     650   .62 0     unknown 0 --- inspect 4.5 2.5  260 0   0     true -32 --- inspect .62   .62   21    .057 0      - --- inspect - --- inspect
ldv-regression/test26_false-unreach-call_true-termination.c false(unreach-call) 1 wit inspect 3.1 1.3 260 32 0      0     false(unreach-call) 1 wit inspect 4.3  2.4  250 0     0   false(unreach-call) 1 --- inspect 7.6   4.5   310   .62 0     false(unreach-call) 1 --- inspect 3.6 2.2  250 0   .29  false(unreach-call) 1 --- inspect .57   .57   20    .045 0      - --- inspect - --- inspect
ldv-regression/test27_false-unreach-call_true-termination.c false(unreach-call) 1 wit inspect 4.4 1.9 280 41 .016  0     false(unreach-call) 1 wit inspect 5.8  3.3  270 0     0   timeout 0 --- inspect 91     58     7000   .97 0     unknown 0 --- inspect 4.1 2.4  250 0   0     error (2) 0 --- inspect .59   .59   21    .057 0      - --- inspect - --- inspect
ldv-regression/test28_false-unreach-call_true-termination.c false(unreach-call) 1 wit inspect 3.0 1.3 260 31 0      0     false(unreach-call) 1 wit inspect 4.9  2.7  250 0     0   false(unreach-call) 1 --- inspect 8.6   5.3   310   .66 0     true -32 --- inspect 3.5 2.1  250 0   .29  false(unreach-call) 1 --- inspect .57   .57   20    .049 .0041 - --- inspect - --- inspect
ldv-regression/test29_false-unreach-call_true-termination.c false(unreach-call) 1 wit inspect 3.0 1.4 270 31 0      0     false(unreach-call) 1 wit inspect 4.3  2.4  250 0     0   false(unreach-call) 1 --- inspect 8.6   4.9   310   .62 0     false(unreach-call) 1 --- inspect 3.8 2.2  250 0   0     false(unreach-call) 1 --- inspect .59   .59   20    .049 0      - --- inspect - --- inspect
ldv-regression/test30_false-unreach-call_true-termination.c false(unreach-call) 1 wit inspect 3.0 1.3 260 29 0      0     false(unreach-call) 1 wit inspect 4.0  2.3  250 0     0   false(unreach-call) 1 --- inspect 8.0   4.8   320   .62 0     false(unreach-call) 1 --- inspect 3.7 2.2  240 0   0     false(unreach-call) 1 --- inspect .57   .57   20    .049 0      - --- inspect - --- inspect
ldv-regression/test01_true-unreach-call_true-termination.c true 2 wit inspect 2.8 1.3 250 29 0      0     - --- inspect - --- inspect - --- inspect - --- inspect true 2 wit inspect 3.5  2.0  250 0   0   true 2 --- inspect 7.1   4.5   310   .62 0  
ldv-regression/test03_true-unreach-call_true-termination.c true 2 wit inspect 2.8 1.3 250 29 0      0     - --- inspect - --- inspect - --- inspect - --- inspect true 2 wit inspect 3.9  2.2  250 0   0   true 2 --- inspect 7.7   4.5   310   .66 0  
ldv-regression/test04_true-unreach-call_true-termination.c true 2 wit inspect 2.9 1.3 250 25 0      0     - --- inspect - --- inspect - --- inspect - --- inspect true 2 wit inspect 4.1  2.3  250 0   0   true 2 --- inspect 9.9   5.8   310   .66 0  
ldv-regression/test05_true-unreach-call_true-termination.c true 2 wit inspect 2.9 1.3 250 27 0      .029 - --- inspect - --- inspect - --- inspect - --- inspect true 2 wit inspect 3.7  2.1  250 0   0   true 2 --- inspect 13     7.5   330   .66 0  
ldv-regression/test07_true-unreach-call_true-termination.c true 2 wit inspect 2.9 1.3 260 26 0      0     - --- inspect - --- inspect - --- inspect - --- inspect true 2 wit inspect 4.0  2.2  250 0   0   true 2 --- inspect 13     7.5   320   .66 0  
ldv-regression/test09_true-unreach-call_true-termination.c true 2 wit inspect 2.9 1.3 260 22 0      0     - --- inspect - --- inspect - --- inspect - --- inspect true 2 wit inspect 3.9  2.2  250 0   0   true 2 --- inspect 9.5   5.7   310   .66 0  
ldv-regression/test10_true-unreach-call_true-termination.c true 2 wit inspect 3.1 1.4 250 32 0      0     - --- inspect - --- inspect - --- inspect - --- inspect true 2 wit inspect 3.7  2.1  260 0   0   true 2 --- inspect 11     6.5   440   .62 0  
ldv-regression/test11_true-unreach-call_true-termination.c true 2 wit inspect 3.0 1.3 260 29 0      0     - --- inspect - --- inspect - --- inspect - --- inspect true 2 wit inspect 4.6  2.6  260 0   0   true 2 --- inspect 8.1   4.6   310   .66 0  
ldv-regression/test13_true-unreach-call_true-termination.c true 2 wit inspect 2.9 1.3 250 24 0      0     - --- inspect - --- inspect - --- inspect - --- inspect true 2 wit inspect 4.2  2.4  250 0   0   true 2 --- inspect 7.2   4.5   300   .62 0  
ldv-regression/test14_true-unreach-call_true-termination.c true 2 wit inspect 2.9 1.3 260 29 0      0     - --- inspect - --- inspect - --- inspect - --- inspect true 2 wit inspect 4.8  2.6  250 0   0   true 2 --- inspect 8.1   5.0   310   .66 0  
ldv-regression/test15_true-unreach-call_true-termination.c true 2 wit inspect 2.9 1.3 250 26 0      0     - --- inspect - --- inspect - --- inspect - --- inspect true 2 wit inspect 4.1  2.3  250 0   0   true 2 --- inspect 9.2   5.4   310   .66 0  
ldv-regression/test16_true-unreach-call_true-termination.c true 2 wit inspect 2.9 1.3 250 26 0      0     - --- inspect - --- inspect - --- inspect - --- inspect true 2 wit inspect 3.7  2.1  250 0   0   true 2 --- inspect 9.6   5.6   310   .66 0  
ldv-regression/test17_true-unreach-call_true-termination.c true 2 wit inspect 2.8 1.3 250 29 0      0     - --- inspect - --- inspect - --- inspect - --- inspect true 2 wit inspect 4.1  2.3  250 0   0   true 2 --- inspect 8.0   4.5   310   .66 0  
ldv-regression/test18_true-unreach-call_true-termination.c true 2 wit inspect 2.8 1.3 250 30 0      0     - --- inspect - --- inspect - --- inspect - --- inspect true 2 wit inspect 3.5  2.0  260 0   0   true 2 --- inspect 8.4   4.8   310   .62 0  
ldv-regression/test19_true-unreach-call_true-termination.c true 2 wit inspect 3.0 1.3 250 27 0      0     - --- inspect - --- inspect - --- inspect - --- inspect true 2 wit inspect 3.6  2.0  250 0   0   true 2 --- inspect 8.9   5.1   310   .66 0  
ldv-regression/test20_true-unreach-call_true-termination.c true 2 wit inspect 2.8 1.3 250 28 0      0     - --- inspect - --- inspect - --- inspect - --- inspect true 2 wit inspect 4.4  2.4  250 0   0   true 2 --- inspect 8.2   4.8   310   .66 0  
ldv-regression/test21_true-unreach-call_true-termination.c true 2 wit inspect 3.1 1.3 260 27 0      0     - --- inspect - --- inspect - --- inspect - --- inspect true 2 wit inspect 4.4  2.5  250 0   0   true 2 --- inspect 9.1   5.1   310   .66 0  
ldv-regression/test22_true-unreach-call.c true 2 wit inspect 11   3.0 510 80 .025  0     - --- inspect - --- inspect - --- inspect - --- inspect true 2 wit inspect 10    6.0  320 0   0   true 2 --- inspect 19     12     480   .62 0  
ldv-regression/test23_true-unreach-call.c true 2 wit inspect 8.3 2.8 440 72 .016  0     - --- inspect - --- inspect - --- inspect - --- inspect true 2 wit inspect 11    6.6  350 0   0   true 2 --- inspect 52     43     700   .62 0  
ldv-regression/test24_true-unreach-call_true-termination.c true 2 wit inspect 6.6 2.3 370 55 .016  0     - --- inspect - --- inspect - --- inspect - --- inspect true 2 wit inspect 7.9  4.5  310 0   0   true 2 --- inspect 32     26     490   .66 0  
ldv-regression/test25_true-unreach-call.c true 2 wit inspect 13   5.3 560 110 .033  0     - --- inspect - --- inspect - --- inspect - --- inspect true 2 wit inspect 16    11    490 0   0   true 2 --- inspect 31     22     500   .62 0  
ldv-regression/test26_true-unreach-call_true-termination.c true 2 wit inspect 3.0 1.3 250 26 0      0     - --- inspect - --- inspect - --- inspect - --- inspect true 2 wit inspect 3.8  2.1  250 0   0   true 2 --- inspect 8.7   4.9   310   .66 0  
ldv-regression/test27_true-unreach-call_true-termination.c true 2 wit inspect 18   11   510 190 .033  0     - --- inspect - --- inspect - --- inspect - --- inspect true 2 wit inspect 33    26    560 0   0   true 2 --- inspect 84     70     810   .62 0  
ldv-regression/test28_true-unreach-call_true-termination.c true 2 wit inspect 3.1 1.4 250 29 0      0     - --- inspect - --- inspect - --- inspect - --- inspect true 2 wit inspect 4.6  2.6  250 0   0   true 2 --- inspect 9.3   5.4   320   .62 0  
ldv-regression/test29_true-unreach-call_true-termination.c true 2 wit inspect 2.9 1.3 260 28 0      0     - --- inspect - --- inspect - --- inspect - --- inspect true 2 wit inspect 3.8  2.1  250 0   0   true 2 --- inspect 8.8   5.5   310   .66 0  
ldv-regression/test30_true-unreach-call_true-termination.c true 2 wit inspect 2.9 1.3 250 29 0      0     - --- inspect - --- inspect - --- inspect - --- inspect true 2 wit inspect 3.4  1.9  250 0   0   true 2 --- inspect 9.9   5.6   330   .66 0  
ddv-machzwd/ddv_machzwd_all_false-unreach-call_true-valid-memsafety.i false(unreach-call) 1 wit inspect 11   3.9 390 99 .029  0     false(unreach-call) 1 wit inspect 14    8.1  420 0     0   error (7) 0 --- inspect 29     16     510   .71 0     unknown 0 --- inspect 6.5 3.6  280 0   .11  false(unreach-call) 1 --- inspect 1.1    1.1    21    .50  0      - --- inspect - --- inspect
ddv-machzwd/ddv_machzwd_inw_false-unreach-call_true-valid-memsafety.i false(unreach-call) 1 wit inspect 10   3.8 510 88 .029  0     false(unreach-call) 1 wit inspect 15    9.0  430 0     0   error (7) 0 --- inspect 32     17     530   .71 0     unknown 0 --- inspect 6.1 3.4  280 0   0     false(unreach-call) 1 --- inspect 1.1    1.1    21    .50  0      - --- inspect - --- inspect
ddv-machzwd/ddv_machzwd_outb_false-unreach-call_true-valid-memsafety.i false(unreach-call) 1 wit inspect 10   3.9 510 98 .029  0     false(unreach-call) 1 wit inspect 13    7.8  410 0     0   error (7) 0 --- inspect 28     16     520   .71 0     unknown 0 --- inspect 6.3 3.5  280 0   0     false(unreach-call) 1 --- inspect 1.1    1.1    21    .50  0      - --- inspect - --- inspect
ddv-machzwd/ddv_machzwd_inb_p_true-unreach-call_false-valid-memtrack.i true 2 wit inspect 96   77   3800 1100 0      0     - --- inspect - --- inspect - --- inspect - --- inspect true 2 wit inspect 11    5.7  420 0   0   error (7) 0 --- inspect 33     18     520   .71 0  
ddv-machzwd/ddv_machzwd_inb_true-unreach-call_false-valid-memtrack.i true 2 wit inspect 96   77   3700 980 0      0     - --- inspect - --- inspect - --- inspect - --- inspect true 2 wit inspect 8.9  4.6  430 0   0   error (7) 0 --- inspect 34     18     520   .75 0  
ddv-machzwd/ddv_machzwd_inl_p_true-unreach-call_false-valid-memtrack.i true 2 wit inspect 96   77   3800 1100 0      0     - --- inspect - --- inspect - --- inspect - --- inspect true 2 wit inspect 11    6.0  430 0   0   error (7) 0 --- inspect 29     17     530   .68 0  
ddv-machzwd/ddv_machzwd_inl_true-unreach-call_false-valid-memtrack.i true 2 wit inspect 97   76   3800 1200 0      0     - --- inspect - --- inspect - --- inspect - --- inspect true 2 wit inspect 10    5.4  420 0   0   error (7) 0 --- inspect 30     17     530   .75 0  
ddv-machzwd/ddv_machzwd_inw_p_true-unreach-call_false-valid-memtrack.i true 2 wit inspect 96   77   3700 1000 0      0     - --- inspect - --- inspect - --- inspect - --- inspect true 2 wit inspect 8.7  4.5  420 0   0   error (7) 0 --- inspect 29     16     550   .75 0  
ddv-machzwd/ddv_machzwd_outb_p_true-unreach-call_false-valid-memtrack.i true 2 wit inspect 96   76   3800 1100 0      0     - --- inspect - --- inspect - --- inspect - --- inspect true 2 wit