Tool CBMC CPAchecker 1.7-svn 29852 ULTIMATE Automizer 0.1.23-635dfa2a CPA-witness2test 1.7-svn 29852 CProver witness2test 0.1 CPAchecker 1.7-svn 29852 ULTIMATE Automizer 0.1.23-635dfa2a
Limits timelimit: 900 s, memlimit: 15000 MB, CPU core limit: 8 timelimit: 90 s, memlimit: 7000 MB, CPU core limit: 2 timelimit: 900 s, memlimit: 7000 MB, CPU core limit: 2
Host apollon*
OS Linux 4.15.0-42-generic
System CPU: Intel Xeon E3-1230 v5 @ 3.40 GHz, cores: 8, frequency: 3.8 GHz, Turbo Boost: disabled; RAM: 33546 MB
Date of execution 2018-12-04 22:48:40 CET 2018-12-06 08:59:15 CET 2018-12-06 10:10:50 CET 2018-12-06 10:22:39 CET 2018-12-12 19:29:48 CET 2018-12-06 07:35:27 CET 2018-12-06 09:23:57 CET
Run set cbmc.sv-comp19_prop-reachsafety.ReachSafety-BitVectors cpa-seq-validate-violation-witnesses-cbmc.sv-comp19_prop-reachsafety.ReachSafety-BitVectors uautomizer-validate-violation-witnesses-cbmc.sv-comp19_prop-reachsafety.ReachSafety-BitVectors cpa-witness2test-validate-violation-witnesses-cbmc.sv-comp19_prop-reachsafety.ReachSafety-BitVectors fshell-witness2test-validate-violation-witnesses-cbmc.sv-comp19_prop-reachsafety.ReachSafety-BitVectors cpa-seq-validate-correctness-witnesses-cbmc.sv-comp19_prop-reachsafety.ReachSafety-BitVectors uautomizer-validate-correctness-witnesses-cbmc.sv-comp19_prop-reachsafety.ReachSafety-BitVectors
Options --graphml-witness witness.graphml -witnessValidation -setprop witness.checkProgramHash=false -heap 5000m -benchmark -setprop cpa.predicate.memoryAllocationsAlwaysSucceed=true -setprop cpa.smg.memoryAllocationFunctions=malloc,__kmalloc,kmalloc,kzalloc,kzalloc_node,ldv_zalloc,ldv_malloc -setprop cpa.smg.arrayAllocationFunctions=calloc,kmalloc_array,kcalloc -setprop cpa.smg.zeroingMemoryAllocation=calloc,kzalloc,kcalloc,kzalloc_node,ldv_zalloc -setprop cpa.smg.deallocationFunctions=free,kfree,kfree_const -witness ../../results-verified/cbmc.2018-12-04_2248.logfiles/${rundefinition_name}.${inputfile_name}.files/witness.graphml --full-output --validate ../../results-verified/cbmc.2018-12-04_2248.logfiles/${rundefinition_name}.${inputfile_name}.files/witness.graphml -setprop witness.checkProgramHash=false -heap 5000m -benchmark -setprop analysis.summaryEdges=true -setprop cpa.callstack.skipVoidRecursion=true -setprop cpa.callstack.skipFunctionPointerRecursion=true -witness ../../results-verified/cbmc.2018-12-04_2248.logfiles/${rundefinition_name}.${inputfile_name}.files/witness.graphml --graphml-witness ../../results-verified/cbmc.2018-12-04_2248.logfiles/${rundefinition_name}.${inputfile_name}.files/witness.graphml -witnessValidation -setprop witness.checkProgramHash=false -heap 5000m -benchmark -setprop cpa.predicate.memoryAllocationsAlwaysSucceed=true -witness ../../results-verified/cbmc.2018-12-04_2248.logfiles/${rundefinition_name}.${inputfile_name}.files/witness.graphml --full-output --validate ../../results-verified/cbmc.2018-12-04_2248.logfiles/${rundefinition_name}.${inputfile_name}.files/witness.graphml
sv-benchmarks/c/ status score witness inspect witness cpu (s) wall (s) mem (MB) energy (J) blkio-w (MB) blkio-r (MB) status score witness inspect witness cpu (s) wall (s) mem (MB) energy blkio-w (MB) blkio-r (MB) status score witness inspect witness cpu (s) wall (s) mem (MB) energy blkio-w (MB) blkio-r (MB) status score witness inspect witness cpu (s) wall (s) mem (MB) energy blkio-w (MB) blkio-r (MB) status score witness inspect witness cpu (s) wall (s) mem (MB) energy blkio-w (MB) blkio-r (MB) status score witness inspect witness cpu (s) wall (s) mem (MB) energy blkio-w (MB) blkio-r (MB) status score witness inspect witness cpu (s) wall (s) mem (MB) energy blkio-w (MB) blkio-r (MB)
bitvector/byte_add_false-unreach-call_true-no-overflow_true-termination.i 1 .17  .15  9.5 1.4  .070  0      1 6.7  3.6  270 0   0   1 60     38     670   .71 0   1 4.7  2.6  270 0   0   1 .68   .68   21    .10  .0041 - -
bitvector/sum02_false-unreach-call_true-no-overflow.i 0 880     880     5300   4000    5.6    0      0 .59 .37 41 0   0   0 .022 .023 5.7 0    0   0 1.0  .64 47 0   0   0 .0046 .0060 .52 0     0      - -
bitvector/byte_add_1_true-unreach-call_true-no-overflow_true-termination.i 1 .11  .10  6.7 1.1  .078  0      - - - - 0 6.8  3.8  330 0   0   0 960     920     990   .72 0  
bitvector/byte_add_2_true-unreach-call_true-no-overflow_true-termination.i 1 .10  .099 6.4 1.1  .078  0      - - - - 0 7.8  4.4  320 0   0   0 960     920     1000   .73 0  
bitvector/gcd_1_true-unreach-call_true-no-overflow.i 1 .24  .23  8.8 2.2  .0082 0      - - - - 0 5.0  2.9  310 0   0   0 960     950     680   .63 0  
bitvector/gcd_2_true-unreach-call_true-no-overflow.i 1 .83  .83  21   13    .057  0      - - - - 0 6.7  3.7  300 0   0   0 960     950     640   .63 0  
bitvector/gcd_3_true-unreach-call_true-no-overflow.i 1 .86  .86  21   9.7  .057  0      - - - - 0 6.1  3.4  300 0   0   0 960     940     2000   .63 0  
bitvector/gcd_4_true-unreach-call_true-no-overflow_true-termination.i 2 .064 .060 6.5 .50 .025  0      - - - - 0 10    7.1  370 0   0   2 44     34     610   .62 0  
bitvector/interleave_bits_true-unreach-call_true-no-overflow.i 2 .16  .15  6.3 .86 .082  0      - - - - 0 5.4  3.0  280 0   0   2 210     200     660   .68 0  
bitvector/jain_1_true-unreach-call_true-no-overflow_false-termination.i 0 880     880     710   5900    7.0    0      - - - - 0 .60 .36 40 0   0   0 .021 .023 5.6 0    0  
bitvector/jain_2_true-unreach-call_true-no-overflow_false-termination.i 0 870     880     1000   5700    8.9    0      - - - - 0 .73 .47 41 0   0   0 .028 .029 5.8 0    0  
bitvector/jain_4_true-unreach-call_true-no-overflow_false-termination.i 0 880     880     1400   7200    12      0      - - - - 0 .61 .38 40 0   0   0 .020 .022 5.6 0    0  
bitvector/jain_5_true-unreach-call_true-no-overflow.i 0 250     250     15000   3700    8.0    0      - - - - 0 .71 .43 41 0   0   0 .028 .029 5.7 0    0  
bitvector/jain_6_true-unreach-call_true-no-overflow_false-termination.i 0 880     880     1400   4400    12      0      - - - - 0 .61 .37 40 0   0   0 .021 .022 5.6 0    0  
bitvector/jain_7_true-unreach-call_true-no-overflow_false-termination.i 0 880     880     1300   6100    13      0      - - - - 0 .65 .39 42 0   0   0 .027 .028 5.6 0    0  
bitvector/modulus_true-unreach-call_true-no-overflow.i 2 250     250     1100   2300    3.4    0      - - - - 0 27    19    630 0   0   2 44     32     540   .62 0  
bitvector/num_conversion_1_true-unreach-call_true-no-overflow.i 2 .11  .10  6.2 .54 .045  0      - - - - 0 5.1  2.8  280 0   0   2 41     26     560   .71 0  
bitvector/num_conversion_2_true-unreach-call_true-no-overflow.i 1 .096 .092 6.9 .71 .053  0      - - - - 0 5.5  3.0  280 0   0   0 960     920     2200   .84 0  
bitvector/parity_true-unreach-call_true-no-overflow.i 1 4.0   4.0   9.1 57    .17   0      - - - - 0 6.5  3.6  280 0   0   0 960     950     1000   .71 0  
bitvector/sum02_true-unreach-call_true-no-overflow.i 0 880     880     5200   4000    5.3    0      - - - - 0 .71 .44 41 0   0   0 .022 .022 5.6 0    0  
bitvector/s3_clnt_1_false-unreach-call_true-no-overflow.BV.c.cil.c 1 4.6   4.5   180   57    .36   0      1 8.5  4.5  310 0   0   1 26     15     430   .75 0   0 9.6  5.2  370 0   0   1 .73   .72   22    .16  0      - -
bitvector/s3_clnt_2_false-unreach-call_true-no-overflow.BV.c.cil.c 1 4.0   4.0   150   53    .39   0      1 8.2  4.4  310 0   0   1 25     14     570   .75 0   0 12    6.2  440 0   0   -32 .73   .73   22    .15  0      - -
bitvector/s3_clnt_3_false-unreach-call_true-no-overflow.BV.c.cil.c 1 .89  .88  52   11    .11   0      1 7.5  4.0  270 0   0   1 25     14     420   .75 0   0 7.4  4.0  300 0   0   1 .72   .72   21    .15  0      - -
bitvector/s3_clnt_1_true-unreach-call_true-no-overflow.BV.c.cil.c 2 19     19     290   250    1.7    0      - - - - 0 530    510    7000 0   0   2 69     39     810   .68 0  
bitvector/s3_clnt_2_true-unreach-call_true-no-overflow.BV.c.cil.c 2 17     17     230   220    1.8    0      - - - - 2 380    370    4700 0   0   2 75     42     990   .71 0  
bitvector/s3_clnt_3_true-unreach-call_true-no-overflow.BV.c.cil.c 2 16     16     220   200    1.8    0      - - - - 2 300    290    4500 0   0   2 47     26     870   .62 0  
bitvector/s3_srvr_1_alt_true-unreach-call_true-no-overflow.BV.c.cil.c 0 880     880     570   10000    1.1    0      - - - - 0 .59 .37 41 0   0   0 .028 .029 5.6 0    0  
bitvector/s3_srvr_1_true-unreach-call_true-no-overflow.BV.c.cil.c 0 880     880     760   5300    8.7    0      - - - - 0 .74 .48 40 0   0   0 .023 .024 5.6 0    0  
bitvector/s3_srvr_2_alt_true-unreach-call_true-no-overflow_false-termination.BV.c.cil.c 0 880     880     660   7000    9.7    0      - - - - 0 .65 .42 41 0   0   0 .027 .028 5.6 0    0  
bitvector/s3_srvr_2_true-unreach-call_true-no-overflow_false-termination.BV.c.cil.c 0 880     880     690   5000    9.9    0      - - - - 0 .72 .44 41 0   0   0 .028 .030 5.6 0    0  
bitvector/s3_srvr_3_alt_true-unreach-call_true-no-overflow.BV.c.cil.c 0 870     880     690   4800    9.0    0      - - - - 0 .76 .46 41 0   0   0 .022 .023 5.6 0    0  
bitvector/s3_srvr_3_true-unreach-call_true-no-overflow.BV.c.cil.c 0 880     880     690   5000    8.8    0      - - - - 0 .64 .39 40 0   0   0 .022 .022 5.6 0    0  
bitvector/soft_float_1_true-unreach-call_true-no-overflow_true-termination.c.cil.c 2 4.7   4.7   35   61    .94   0      - - - - 0 52    43    1000 0   0   2 170     140     840   .68 0  
bitvector/soft_float_2_true-unreach-call_true-no-overflow_true-termination.c.cil.c 2 3.0   3.0   35   38    .98   0      - - - - 0 13    6.9  520 0   0   2 47     30     710   .66 0  
bitvector/soft_float_3_true-unreach-call_true-no-overflow_true-termination.c.cil.c 1 3.0   3.0   36   39    .98   0      - - - - 0 12    6.5  510 0   0   0 960     890     780   1.6  0  
bitvector/soft_float_4_true-unreach-call_true-no-overflow_true-termination.c.cil.c 2 7.8   7.8   42   95    .93   0      - - - - 0 240    240    810 0   0   2 390     350     780   .71 0  
bitvector/soft_float_5_true-unreach-call_true-no-overflow_true-termination.c.cil.c 2 3.0   3.0   35   38    .98   0      - - - - 0 13    7.0  520 0   0   2 37     21     540   .66 0  
bitvector-regression/implicitfloatconversion_false-unreach-call_true-termination.c 1 .067 .057 8.9 .46 .0082 0      1 4.7  2.6  250 0   0   1 13     7.6   300   .71 0   1 3.7  2.2  250 0   0   1 .56   .56   20    .041 .0082 - -
bitvector-regression/implicitunsignedconversion_false-unreach-call_true-termination.c 1 .066 .055 9.8 .48 .0082 0      1 4.1  2.3  250 0   0   1 6.6   4.2   290   .62 0   1 3.5  2.0  240 0   0   1 .56   .56   20    .041 0      - -
bitvector-regression/integerpromotion_false-unreach-call_true-termination.c 1 .068 .058 9.5 .37 .0082 0      1 4.7  2.6  250 0   0   1 12     7.3   290   .60 0   1 3.5  2.1  250 0   0   1 .57   .57   20    .041 0      - -
bitvector-regression/recHanoi03_false-unreach-call_true-termination.c 1 .30  .29  9.8 4.1  .12   0      1 57    41    2000 0   0   -32 7.5   4.2   310   .66 0   1 6.0  3.4  280 0   0   1 .61   .61   21    .049 0      - -
bitvector-regression/signextension2_false-unreach-call_true-termination.c 1 .073 .063 9.7 .43 .0082 0      1 4.7  2.6  250 0   0   -32 6.5   3.7   290   .66 0   1 3.7  2.1  250 0   0   1 .60   .60   20    .045 0      - -
bitvector-regression/signextension_false-unreach-call_true-termination.c 1 .14  .12  9.8 .40 .0082 0      1 4.5  2.5  250 0   0   -32 6.6   3.7   300   .62 0   1 3.7  2.2  250 0   0   1 .56   .56   20    .045 0      - -
bitvector-regression/implicitunsignedconversion_true-unreach-call_true-termination.c 2 .094 .088 6.1 .23 .0082 0      - - - - 2 3.4  1.9  250 0   0   2 9.0   5.3   300   .66 0  
bitvector-regression/integerpromotion_true-unreach-call_true-termination.c 2 .052 .050 6.7 .37 .0082 0      - - - - 2 4.2  2.4  250 0   0   2 13     7.6   300   .75 0  
bitvector-regression/signextension2_true-unreach-call_true-termination.c 2 .055 .052 6.8 .29 .0082 0      - - - - 2 4.2  2.3  250 0   0   2 6.9   4.3   300   .66 0  
bitvector-regression/signextension_true-unreach-call_true-termination.c 2 .058 .055 6.4 .33 .0082 0      - - - - 2 3.8  2.1  250 0   0   2 10     5.9   320   .66 0  
bitvector-loops/diamond_false-unreach-call2.i 1 .085 .079 9.7 .69 .0082 0      1 4.7  2.6  250 0   0   1 7.8   4.4   310   .62 0   1 4.8  2.7  250 0   0   1 .59   .58   20    .049 0      - -
bitvector-loops/overflow_false-unreach-call1.i 0 270     270     15000   4200    .73   .0041 0 .59 .37 41 0   0   0 .021 .022 5.6 0    0   0 .92 .61 47 0   0   0 .0044 .0053 .53 0     0      - -
bitvector-loops/verisec_sendmail__tTflag_arr_one_loop_false-unreach-call_true-termination.i 1 .14  .13  9.6 1.5  .094  0      1 6.9  3.9  290 0   0   0 97     87     820   1.5  0   0 4.3  2.5  260 0   0   0 .60   .60   21    .037 .0041 - -
sv-benchmarks/c/ status score witness inspect witness cpu (s) wall (s) mem (MB) energy (J) blkio-w (MB) blkio-r (MB) status score witness inspect witness cpu (s) wall (s) mem (MB) energy blkio-w (MB) blkio-r (MB) status score witness inspect witness cpu (s) wall (s) mem (MB) energy blkio-w (MB) blkio-r (MB) status score witness inspect witness cpu (s) wall (s) mem (MB) energy blkio-w (MB) blkio-r (MB) status score witness inspect witness cpu (s) wall (s) mem (MB) energy blkio-w (MB) blkio-r (MB) status score witness inspect witness cpu (s) wall (s) mem (MB) energy blkio-w (MB) blkio-r (MB) status score witness inspect witness cpu (s) wall (s) mem (MB) energy blkio-w (MB) blkio-r (MB)
total 50 50 12000   12000   53000 86000 130   .0041 14 12 120 77 5000 0   0   14 -88 290 200 5000 8.9 0   14 8 68 38 3500 0   0   14 -22 7.5  7.5  250 .91 .016 36 12 1700 1500 25000 0   0   36 30 8900 8400 19000 17 0  
    correct results 27 42 330   330   2500 3300 14   0      12 12 120 76 4900 0   0   8 8 180 100 3300 5.5 0   8 8 34 19 2000 0   0   10 10 6.2  6.2  210 .72 .012 6 12 700 670 10000 0   0   15 30 1200 960 9100 10 0  
        correct true 15 30 320   320   2000 3200 13   0      0 0 0 0 6 12 700 670 10000 0   0   15 30 1200 960 9100 10 0  
        correct false 12 12 11   10   470 130 1.2 0      12 12 120 76 4900 0   0   8 8 180 100 3300 5.5 0   8 8 34 19 2000 0   0   10 10 6.2  6.2  210 .72 .012 0 0
    correct-unconfimed results 8 8 9.3 9.3 120 120 1.5 0      0 0 0 0 0 0
        correct-unconfirmed true 8 8 9.3 9.3 120 120 1.5 0      0 0 0 0 0 0
        correct-unconfirmed false 0 0 0 0 0 0 0
    incorrect results 0 0 3 -96 21 12 890 1.9 0   0 1 -32 .73 .73 22 .15 0     0 0
        incorrect true 0 0 3 -96 21 12 890 1.9 0   0 1 -32 .73 .73 22 .15 0     0 0
        incorrect false 0 0 0 0 0 0 0
score (50 tasks, max score: 86) 50 12 -88 8 -22 12 30
Run set cbmc.sv-comp19_prop-reachsafety.ReachSafety-BitVectors cpa-seq-validate-violation-witnesses-cbmc.sv-comp19_prop-reachsafety.ReachSafety-BitVectors uautomizer-validate-violation-witnesses-cbmc.sv-comp19_prop-reachsafety.ReachSafety-BitVectors cpa-witness2test-validate-violation-witnesses-cbmc.sv-comp19_prop-reachsafety.ReachSafety-BitVectors fshell-witness2test-validate-violation-witnesses-cbmc.sv-comp19_prop-reachsafety.ReachSafety-BitVectors cpa-seq-validate-correctness-witnesses-cbmc.sv-comp19_prop-reachsafety.ReachSafety-BitVectors uautomizer-validate-correctness-witnesses-cbmc.sv-comp19_prop-reachsafety.ReachSafety-BitVectors