Tool CBMC Path 5.10 () CPAchecker 1.7-svn 29852 ULTIMATE Automizer 0.1.23-635dfa2a CPA-witness2test 1.7-svn 29852 CProver witness2test 0.1 CPAchecker 1.7-svn 29852 ULTIMATE Automizer 0.1.23-635dfa2a
Limits timelimit: 900 s, memlimit: 15000 MB, CPU core limit: 8 timelimit: 90 s, memlimit: 7000 MB, CPU core limit: 2 timelimit: 900 s, memlimit: 7000 MB, CPU core limit: 2
Host apollon*
OS Linux 4.15.0-42-generic
System CPU: Intel Xeon E3-1230 v5 @ 3.40 GHz, cores: 8, frequency: 3.8 GHz, Turbo Boost: disabled; RAM: 33546 MB
Date of execution 2018-12-04 22:45:10 CET 2018-12-06 08:53:36 CET 2018-12-06 10:12:52 CET 2018-12-06 10:22:39 CET 2018-12-12 19:23:37 CET 2018-12-06 07:24:45 CET 2018-12-06 09:28:06 CET
Run set cbmc-path.sv-comp19_prop-reachsafety.ReachSafety-BitVectors cpa-seq-validate-violation-witnesses-cbmc-path.sv-comp19_prop-reachsafety.ReachSafety-BitVectors uautomizer-validate-violation-witnesses-cbmc-path.sv-comp19_prop-reachsafety.ReachSafety-BitVectors cpa-witness2test-validate-violation-witnesses-cbmc-path.sv-comp19_prop-reachsafety.ReachSafety-BitVectors fshell-witness2test-validate-violation-witnesses-cbmc-path.sv-comp19_prop-reachsafety.ReachSafety-BitVectors cpa-seq-validate-correctness-witnesses-cbmc-path.sv-comp19_prop-reachsafety.ReachSafety-BitVectors uautomizer-validate-correctness-witnesses-cbmc-path.sv-comp19_prop-reachsafety.ReachSafety-BitVectors
Options --graphml-witness witness.graphml -witnessValidation -setprop witness.checkProgramHash=false -heap 5000m -benchmark -setprop cpa.predicate.memoryAllocationsAlwaysSucceed=true -setprop cpa.smg.memoryAllocationFunctions=malloc,__kmalloc,kmalloc,kzalloc,kzalloc_node,ldv_zalloc,ldv_malloc -setprop cpa.smg.arrayAllocationFunctions=calloc,kmalloc_array,kcalloc -setprop cpa.smg.zeroingMemoryAllocation=calloc,kzalloc,kcalloc,kzalloc_node,ldv_zalloc -setprop cpa.smg.deallocationFunctions=free,kfree,kfree_const -witness ../../results-verified/cbmc-path.2018-12-04_2245.logfiles/${rundefinition_name}.${inputfile_name}.files/witness.graphml --full-output --validate ../../results-verified/cbmc-path.2018-12-04_2245.logfiles/${rundefinition_name}.${inputfile_name}.files/witness.graphml -setprop witness.checkProgramHash=false -heap 5000m -benchmark -setprop analysis.summaryEdges=true -setprop cpa.callstack.skipVoidRecursion=true -setprop cpa.callstack.skipFunctionPointerRecursion=true -witness ../../results-verified/cbmc-path.2018-12-04_2245.logfiles/${rundefinition_name}.${inputfile_name}.files/witness.graphml --graphml-witness ../../results-verified/cbmc-path.2018-12-04_2245.logfiles/${rundefinition_name}.${inputfile_name}.files/witness.graphml -witnessValidation -setprop witness.checkProgramHash=false -heap 5000m -benchmark -setprop cpa.predicate.memoryAllocationsAlwaysSucceed=true -witness ../../results-verified/cbmc-path.2018-12-04_2245.logfiles/${rundefinition_name}.${inputfile_name}.files/witness.graphml --full-output --validate ../../results-verified/cbmc-path.2018-12-04_2245.logfiles/${rundefinition_name}.${inputfile_name}.files/witness.graphml
sv-benchmarks/c/ status score witness inspect witness cpu (s) wall (s) mem (MB) energy (J) blkio-w (MB) blkio-r (MB) status score witness inspect witness cpu (s) wall (s) mem (MB) energy blkio-w (MB) blkio-r (MB) status score witness inspect witness cpu (s) wall (s) mem (MB) energy blkio-w (MB) blkio-r (MB) status score witness inspect witness cpu (s) wall (s) mem (MB) energy blkio-w (MB) blkio-r (MB) status score witness inspect witness cpu (s) wall (s) mem (MB) energy blkio-w (MB) blkio-r (MB) status score witness inspect witness cpu (s) wall (s) mem (MB) energy blkio-w (MB) blkio-r (MB) status score witness inspect witness cpu (s) wall (s) mem (MB) energy blkio-w (MB) blkio-r (MB)
bitvector/byte_add_false-unreach-call_true-no-overflow_true-termination.i 1 .64  .62  37   8.0  1.8    0      -32 5.2  2.8  260 0   0   1 50     30     650   .68 0   1 4.7  2.7  260 0   3.6   1 .68   .68   21    .10  0      - -
bitvector/sum02_false-unreach-call_true-no-overflow.i 0 880     880     110   13000    410      0      0 .72 .44 41 0   0   0 .022 .023 5.6 0    0   0 .95 .61 48 0   0     0 .0018 .0023 .52 0     0      - -
bitvector/byte_add_1_true-unreach-call_true-no-overflow_true-termination.i 1 .30  .30  12   3.6  1.4    0      - - - - 0 6.3  3.5  300 0   0   0 960     920     990   1.7  0     
bitvector/byte_add_2_true-unreach-call_true-no-overflow_true-termination.i 1 .33  .33  12   4.4  1.4    0      - - - - 0 7.9  4.4  290 0   0   0 960     920     1000   1.7  0     
bitvector/gcd_1_true-unreach-call_true-no-overflow.i 1 .28  .28  9.9 3.7  .11   0      - - - - 0 6.2  3.5  310 0   0   0 960     940     660   .74 0     
bitvector/gcd_2_true-unreach-call_true-no-overflow.i 1 3.6   3.6   26   50    1.4    0      - - - - 0 5.6  3.1  290 0   0   0 960     950     670   .70 0     
bitvector/gcd_3_true-unreach-call_true-no-overflow.i 1 3.7   3.7   25   52    1.4    0      - - - - 0 4.8  2.7  290 0   0   0 960     950     960   .75 .0082
bitvector/gcd_4_true-unreach-call_true-no-overflow_true-termination.i 2 .063 .060 6.3 .41 .012  0      - - - - 0 9.5  6.8  390 0   0   2 37     27     620   .62 0     
bitvector/interleave_bits_true-unreach-call_true-no-overflow.i 2 .12  .11  6.8 1.2  .082  0      - - - - 0 7.1  3.8  290 0   0   2 210     200     670   .68 0     
bitvector/jain_1_true-unreach-call_true-no-overflow_false-termination.i 0 300     300     15000   3700    1500      0      - - - - 0 .78 .46 42 0   0   0 .026 .028 5.6 0    0     
bitvector/jain_2_true-unreach-call_true-no-overflow_false-termination.i 0 420     420     15000   5200    1500      .0082 - - - - 0 .61 .38 41 0   0   0 .024 .024 5.6 0    0     
bitvector/jain_4_true-unreach-call_true-no-overflow_false-termination.i 0 540     530     15000   7600    1500      .0041 - - - - 0 .76 .47 43 0   0   0 .026 .027 5.6 0    0     
bitvector/jain_5_true-unreach-call_true-no-overflow.i 0 190     190     15000   2300    .61   0      - - - - 0 .59 .36 41 0   0   0 .021 .022 5.6 0    0     
bitvector/jain_6_true-unreach-call_true-no-overflow_false-termination.i 0 540     540     15000   8100    1500      .0082 - - - - 0 .77 .49 40 0   0   0 .021 .022 5.6 0    0     
bitvector/jain_7_true-unreach-call_true-no-overflow_false-termination.i 0 360     360     15000   4600    1500      .012  - - - - 0 .62 .39 40 0   0   0 .027 .028 5.6 0    0     
bitvector/modulus_true-unreach-call_true-no-overflow.i 0 880     880     9600   12000    640      0      - - - - 0 .74 .46 41 0   0   0 .025 .026 5.6 0    0     
bitvector/num_conversion_1_true-unreach-call_true-no-overflow.i 2 .086 .082 6.6 .72 .016  0      - - - - 0 4.8  2.6  280 0   0   2 33     21     560   .71 0     
bitvector/num_conversion_2_true-unreach-call_true-no-overflow.i 1 1.0   1.0   63   12    6.5    0      - - - - 0 5.8  3.2  280 0   0   0 960     930     2200   1.6  0     
bitvector/parity_true-unreach-call_true-no-overflow.i 1 4.0   4.0   9.9 54    2.4    0      - - - - 0 6.3  3.4  290 0   0   0 960     950     1100   1.6  0     
bitvector/sum02_true-unreach-call_true-no-overflow.i 0 880     880     110   11000    410      0      - - - - 0 .72 .43 40 0   0   0 .021 .023 5.6 0    0     
bitvector/s3_clnt_1_false-unreach-call_true-no-overflow.BV.c.cil.c 0 160     160     15000   2100    .025  0      0 .76 .46 41 0   0   0 .021 .023 5.8 0    0   0 .94 .60 47 0   0     0 .0017 .0029 .54 0     0      - -
bitvector/s3_clnt_2_false-unreach-call_true-no-overflow.BV.c.cil.c 0 160     160     15000   1700    .025  0      0 .78 .47 40 0   0   0 .022 .022 5.6 0    0   0 .97 .63 47 0   0     0 .0019 .0025 .52 0     0      - -
bitvector/s3_clnt_3_false-unreach-call_true-no-overflow.BV.c.cil.c 1 17     17     2000   220    2.5    0      -32 5.8  3.1  270 0   0   1 20     11     380   .75 0   0 6.2  3.4  280 0   .012 -32 .71   .71   21    .15  0      - -
bitvector/s3_clnt_1_true-unreach-call_true-no-overflow.BV.c.cil.c 0 160     160     15000   1900    .025  0      - - - - 0 .65 .40 40 0   0   0 .023 .024 5.6 0    0     
bitvector/s3_clnt_2_true-unreach-call_true-no-overflow.BV.c.cil.c 0 160     160     15000   2000    .025  .0041 - - - - 0 .76 .46 41 0   0   0 .022 .023 5.7 0    0     
bitvector/s3_clnt_3_true-unreach-call_true-no-overflow.BV.c.cil.c 0 130     130     15000   1600    .033  .0041 - - - - 0 .61 .37 41 0   0   0 .026 .028 5.7 0    0     
bitvector/s3_srvr_1_alt_true-unreach-call_true-no-overflow.BV.c.cil.c 0 110     110     15000   1300    .033  0      - - - - 0 .80 .48 42 0   0   0 .021 .022 5.6 0    0     
bitvector/s3_srvr_1_true-unreach-call_true-no-overflow.BV.c.cil.c 0 110     110     15000   1500    .033  0      - - - - 0 .73 .44 40 0   0   0 .020 .021 5.6 0    0     
bitvector/s3_srvr_2_alt_true-unreach-call_true-no-overflow_false-termination.BV.c.cil.c 0 370     370     15000   3900    .025  0      - - - - 0 .79 .48 42 0   0   0 .023 .025 5.6 0    0     
bitvector/s3_srvr_2_true-unreach-call_true-no-overflow_false-termination.BV.c.cil.c 0 390     380     15000   3800    .025  .0041 - - - - 0 .58 .35 40 0   0   0 .024 .025 5.6 0    0     
bitvector/s3_srvr_3_alt_true-unreach-call_true-no-overflow.BV.c.cil.c 0 110     110     15000   1500    .033  0      - - - - 0 .72 .44 41 0   0   0 .030 .031 5.6 0    0     
bitvector/s3_srvr_3_true-unreach-call_true-no-overflow.BV.c.cil.c 0 110     110     15000   1500    .033  .0041 - - - - 0 .73 .44 41 0   0   0 .024 .025 5.6 0    0     
bitvector/soft_float_1_true-unreach-call_true-no-overflow_true-termination.c.cil.c 0 870     880     4900   13000    2400      0      - - - - 0 .59 .37 41 0   0   0 .022 .024 5.6 0    0     
bitvector/soft_float_2_true-unreach-call_true-no-overflow_true-termination.c.cil.c 0 870     880     1300   9600    2500      .0041 - - - - 0 .61 .37 40 0   0   0 .026 .026 5.6 0    0     
bitvector/soft_float_3_true-unreach-call_true-no-overflow_true-termination.c.cil.c 0 870     880     1800   11000    2300      .0041 - - - - 0 .77 .46 40 0   0   0 .026 .026 5.6 0    0     
bitvector/soft_float_4_true-unreach-call_true-no-overflow_true-termination.c.cil.c 0 870     880     3500   12000    2100      .0041 - - - - 0 .74 .47 40 0   0   0 .022 .023 5.6 0    0     
bitvector/soft_float_5_true-unreach-call_true-no-overflow_true-termination.c.cil.c 0 870     880     1300   9100    2300      .0082 - - - - 0 .65 .41 41 0   0   0 .024 .025 5.5 0    0     
bitvector-regression/implicitfloatconversion_false-unreach-call_true-termination.c 1 .062 .052 9.6 .42 .0082 0      1 4.5  2.5  250 0   0   1 13     7.3   300   .68 0   1 3.7  2.2  250 0   8.2   1 .57   .57   20    .041 0      - -
bitvector-regression/implicitunsignedconversion_false-unreach-call_true-termination.c 1 .064 .054 9.1 .42 .0082 0      1 4.6  2.5  250 0   0   1 6.8   3.8   290   .66 0   1 3.3  1.9  240 0   0     1 .56   .56   20    .041 .0041 - -
bitvector-regression/integerpromotion_false-unreach-call_true-termination.c 1 .066 .055 9.1 .42 .0082 0      1 4.4  2.5  250 0   0   1 13     7.7   300   .75 0   1 3.5  2.1  250 0   .012 1 .60   .60   20    .041 .0041 - -
bitvector-regression/recHanoi03_false-unreach-call_true-termination.c 1 .74  .73  9.6 12    1.4    0      1 52    36    2000 0   0   -32 7.8   4.3   310   .66 0   1 5.8  3.2  280 0   0     1 .60   .63   21    .049 .0041 - -
bitvector-regression/signextension2_false-unreach-call_true-termination.c 1 .071 .060 9.7 .38 .0082 0      1 4.2  2.4  250 0   0   -32 7.2   4.4   290   .66 0   1 3.7  2.2  250 0   3.8   1 .57   .57   20    .045 0      - -
bitvector-regression/signextension_false-unreach-call_true-termination.c 1 .068 .060 9.5 .49 .0082 0      1 4.0  2.2  250 0   0   -32 7.2   4.1   290   .66 0   1 3.6  2.1  250 0   0     1 .56   .56   20    .045 0      - -
bitvector-regression/implicitunsignedconversion_true-unreach-call_true-termination.c 0 .044 .043 6.5 .25 .0082 0      - - - - 0 .60 .37 42 0   0   0 4.9   3.1   260   .61 0     
bitvector-regression/integerpromotion_true-unreach-call_true-termination.c 0 .042 .041 6.1 .28 .0082 0      - - - - 0 .68 .43 43 0   0   0 5.1   2.8   260   .61 0     
bitvector-regression/signextension2_true-unreach-call_true-termination.c 0 .043 .042 6.2 .24 .0082 0      - - - - 0 .84 .51 43 0   0   0 5.5   3.0   260   .61 0     
bitvector-regression/signextension_true-unreach-call_true-termination.c 0 .037 .036 6.2 .29 .0082 0      - - - - 0 .84 .50 44 0   0   0 5.9   3.2   260   .61 0     
bitvector-loops/diamond_false-unreach-call2.i 1 2.8   2.8   420   36    1.3    0      -32 4.6  2.5  250 0   0   1 7.4   4.2   310   .66 0   1 4.0  2.2  250 0   0     1 .60   .59   20    .049 0      - -
bitvector-loops/overflow_false-unreach-call1.i 0 200     200     15000   3000    .73   .0041 0 .59 .37 40 0   0   0 .021 .021 5.6 0    0   0 .91 .60 47 0   0     0 .0045 .0055 .40 0     0      - -
bitvector-loops/verisec_sendmail__tTflag_arr_one_loop_false-unreach-call_true-termination.i 0 .22  .22  9.3 2.6  .45   0      -32 4.8  2.6  260 0   0   0 97     86     820   1.2  0   0 4.3  2.5  270 0   0     0 .59   .59   21    .037 0      - -
sv-benchmarks/c/ status score witness inspect witness cpu (s) wall (s) mem (MB) energy (J) blkio-w (MB) blkio-r (MB) status score witness inspect witness cpu (s) wall (s) mem (MB) energy blkio-w (MB) blkio-r (MB) status score witness inspect witness cpu (s) wall (s) mem (MB) energy blkio-w (MB) blkio-r (MB) status score witness inspect witness cpu (s) wall (s) mem (MB) energy blkio-w (MB) blkio-r (MB) status score witness inspect witness cpu (s) wall (s) mem (MB) energy blkio-w (MB) blkio-r (MB) status score witness inspect witness cpu (s) wall (s) mem (MB) energy blkio-w (MB) blkio-r (MB) status score witness inspect witness cpu (s) wall (s) mem (MB) energy blkio-w (MB) blkio-r (MB)
total 50 22 12000    12000    300000   150000   21000    .074 14 -122 97 61 4500 0   0   14 -90 230 160 4000 7.4 0   14 8 46 27 2700 0   16 14 -24 6.1  6.1  210 .60 .012 36 0 83 48 4100 0   0   36 6 7000 6800 11000 13   .0082
    correct results 12 15 22    22    2600   280   7.1  0     6 6 74 48 3300 0   0   6 6 110 65 2200 4.2 0   8 8 32 19 2000 0   16 8 8 4.7  4.8  160 .41 .012 0 3 6 280 250 1900 2.0 0     
        correct true 3 6 .26 .25 20   2.3 .11 0     0 0 0 0 0 3 6 280 250 1900 2.0 0     
        correct false 9 9 22    22    2500   280   7.0  0     6 6 74 48 3300 0   0   6 6 110 65 2200 4.2 0   8 8 32 19 2000 0   16 8 8 4.7  4.8  160 .41 .012 0 0
    correct-unconfimed results 8 7 14    13    170   180   15    0     0 0 0 0 0 0
        correct-unconfirmed true 7 7 13    13    160   180   15    0     0 0 0 0 0 0
        correct-unconfirmed false 1 0 .22 .22 9.3 2.6 .45 0     0 0 0 0 0 0
    incorrect results 0 4 -128 20 11 1000 0   0   3 -96 22 13 890 2.0 0   0 1 -32 .71 .71 21 .15 0     0 0
        incorrect true 0 4 -128 20 11 1000 0   0   3 -96 22 13 890 2.0 0   0 1 -32 .71 .71 21 .15 0     0 0
        incorrect false 0 0 0 0 0 0 0
score (50 tasks, max score: 86) 22 -122 -90 8 -24 0 6
Run set cbmc-path.sv-comp19_prop-reachsafety.ReachSafety-BitVectors cpa-seq-validate-violation-witnesses-cbmc-path.sv-comp19_prop-reachsafety.ReachSafety-BitVectors uautomizer-validate-violation-witnesses-cbmc-path.sv-comp19_prop-reachsafety.ReachSafety-BitVectors cpa-witness2test-validate-violation-witnesses-cbmc-path.sv-comp19_prop-reachsafety.ReachSafety-BitVectors fshell-witness2test-validate-violation-witnesses-cbmc-path.sv-comp19_prop-reachsafety.ReachSafety-BitVectors cpa-seq-validate-correctness-witnesses-cbmc-path.sv-comp19_prop-reachsafety.ReachSafety-BitVectors uautomizer-validate-correctness-witnesses-cbmc-path.sv-comp19_prop-reachsafety.ReachSafety-BitVectors