Tool 2LS 0.7.2-sv-comp19 CPAchecker 1.7-svn 29852 ULTIMATE Automizer 0.1.23-635dfa2a CPA-witness2test 1.7-svn 29852 CProver witness2test 0.1 CPAchecker 1.7-svn 29852 ULTIMATE Automizer 0.1.23-635dfa2a
Limits timelimit: 900 s, memlimit: 15000 MB, CPU core limit: 8 timelimit: 90 s, memlimit: 7000 MB, CPU core limit: 2 timelimit: 900 s, memlimit: 7000 MB, CPU core limit: 2
Host apollon*
OS Linux 4.15.0-42-generic
System CPU: Intel Xeon E3-1230 v5 @ 3.40 GHz, cores: 8, frequency: 3.8 GHz, Turbo Boost: disabled; RAM: 33546 MB
Date of execution 2018-12-04 22:44:17 CET 2018-12-06 09:36:46 CET 2018-12-06 10:26:50 CET 2018-12-06 10:31:50 CET 2018-12-12 19:28:33 CET 2018-12-06 06:59:33 CET 2018-12-06 09:46:05 CET
Run set 2ls.sv-comp19_prop-reachsafety.ReachSafety-BitVectors cpa-seq-validate-violation-witnesses-2ls.sv-comp19_prop-reachsafety.ReachSafety-BitVectors uautomizer-validate-violation-witnesses-2ls.sv-comp19_prop-reachsafety.ReachSafety-BitVectors cpa-witness2test-validate-violation-witnesses-2ls.sv-comp19_prop-reachsafety.ReachSafety-BitVectors fshell-witness2test-validate-violation-witnesses-2ls.sv-comp19_prop-reachsafety.ReachSafety-BitVectors cpa-seq-validate-correctness-witnesses-2ls.sv-comp19_prop-reachsafety.ReachSafety-BitVectors uautomizer-validate-correctness-witnesses-2ls.sv-comp19_prop-reachsafety.ReachSafety-BitVectors
Options --graphml-witness witness.graphml -witnessValidation -setprop witness.checkProgramHash=false -heap 5000m -benchmark -setprop cpa.predicate.memoryAllocationsAlwaysSucceed=true -setprop cpa.smg.memoryAllocationFunctions=malloc,__kmalloc,kmalloc,kzalloc,kzalloc_node,ldv_zalloc,ldv_malloc -setprop cpa.smg.arrayAllocationFunctions=calloc,kmalloc_array,kcalloc -setprop cpa.smg.zeroingMemoryAllocation=calloc,kzalloc,kcalloc,kzalloc_node,ldv_zalloc -setprop cpa.smg.deallocationFunctions=free,kfree,kfree_const -witness ../../results-verified/2ls.2018-12-04_2244.logfiles/${rundefinition_name}.${inputfile_name}.files/witness.graphml --full-output --validate ../../results-verified/2ls.2018-12-04_2244.logfiles/${rundefinition_name}.${inputfile_name}.files/witness.graphml -setprop witness.checkProgramHash=false -heap 5000m -benchmark -setprop analysis.summaryEdges=true -setprop cpa.callstack.skipVoidRecursion=true -setprop cpa.callstack.skipFunctionPointerRecursion=true -witness ../../results-verified/2ls.2018-12-04_2244.logfiles/${rundefinition_name}.${inputfile_name}.files/witness.graphml --graphml-witness ../../results-verified/2ls.2018-12-04_2244.logfiles/${rundefinition_name}.${inputfile_name}.files/witness.graphml -witnessValidation -setprop witness.checkProgramHash=false -heap 5000m -benchmark -setprop cpa.predicate.memoryAllocationsAlwaysSucceed=true -witness ../../results-verified/2ls.2018-12-04_2244.logfiles/${rundefinition_name}.${inputfile_name}.files/witness.graphml --full-output --validate ../../results-verified/2ls.2018-12-04_2244.logfiles/${rundefinition_name}.${inputfile_name}.files/witness.graphml
sv-benchmarks/c/ status score witness inspect witness cpu (s) wall (s) mem (MB) energy (J) blkio-w (MB) blkio-r (MB) status score witness inspect witness cpu (s) wall (s) mem (MB) energy blkio-w (MB) blkio-r (MB) status score witness inspect witness cpu (s) wall (s) mem (MB) energy blkio-w (MB) blkio-r (MB) status score witness inspect witness cpu (s) wall (s) mem (MB) energy blkio-w (MB) blkio-r (MB) status score witness inspect witness cpu (s) wall (s) mem (MB) energy blkio-w (MB) blkio-r (MB) status score witness inspect witness cpu (s) wall (s) mem (MB) energy blkio-w (MB) blkio-r (MB) status score witness inspect witness cpu (s) wall (s) mem (MB) energy blkio-w (MB) blkio-r (MB)
bitvector/byte_add_false-unreach-call_true-no-overflow_true-termination.i 1 .36  .35  24 3.7  0     0     -32 5.9  3.2  260 0   0   1 70     53     610   .68 0   1 4.5  2.5  260 0   0   1 .68   .67   21    .094 0      - -
bitvector/sum02_false-unreach-call_true-no-overflow.i 0 900     900     1400 12000    .016 0     0 .65 .39 42 0   0   0 .023 .025 5.6 0    0   0 1.0  .65 49 0   0   0 .0050 .019  .53 0     0      - -
bitvector/byte_add_1_true-unreach-call_true-no-overflow_true-termination.i 2 .36  .36  24 3.8  0     0     - - - - 2 10    5.5  390 0   0   0 960     920     990   1.6  0  
bitvector/byte_add_2_true-unreach-call_true-no-overflow_true-termination.i 2 .34  .34  24 4.1  0     0     - - - - 2 9.8  5.3  390 0   0   0 960     930     990   .70 0  
bitvector/gcd_1_true-unreach-call_true-no-overflow.i 2 .24  .24  24 2.5  0     0     - - - - 2 9.7  7.8  320 0   0   0 960     940     4300   .75 0  
bitvector/gcd_2_true-unreach-call_true-no-overflow.i 2 .68  .67  27 8.5  0     0     - - - - 2 150    150    560 0   0   0 960     950     710   .62 0  
bitvector/gcd_3_true-unreach-call_true-no-overflow.i 2 .67  .67  25 8.1  0     0     - - - - 2 130    120    560 0   0   0 960     950     1800   1.6  0  
bitvector/gcd_4_true-unreach-call_true-no-overflow_true-termination.i 2 .34  .34  23 3.8  0     0     - - - - 2 8.7  5.6  320 0   0   2 37     29     580   .62 0  
bitvector/interleave_bits_true-unreach-call_true-no-overflow.i 2 .47  .47  44 5.3  0     0     - - - - 2 13    8.5  380 0   0   2 190     180     690   .68 0  
bitvector/jain_1_true-unreach-call_true-no-overflow_false-termination.i 0 900     900     1400 12000    .016 0     - - - - 0 .77 .47 40 0   0   0 .020 .021 5.6 0    0  
bitvector/jain_2_true-unreach-call_true-no-overflow_false-termination.i 0 900     900     1400 11000    .016 0     - - - - 0 .63 .38 42 0   0   0 .039 .040 5.5 0    0  
bitvector/jain_4_true-unreach-call_true-no-overflow_false-termination.i 0 900     900     1900 13000    .016 0     - - - - 0 .78 .47 41 0   0   0 .028 .034 5.7 0    0  
bitvector/jain_5_true-unreach-call_true-no-overflow.i 0 900     900     1400 13000    .016 0     - - - - 0 .81 .49 41 0   0   0 .021 .022 5.6 0    0  
bitvector/jain_6_true-unreach-call_true-no-overflow_false-termination.i 0 900     900     1800 10000    .016 0     - - - - 0 .77 .47 41 0   0   0 .020 .021 5.7 0    0  
bitvector/jain_7_true-unreach-call_true-no-overflow_false-termination.i 0 900     900     1600 13000    .016 0     - - - - 0 .82 .50 41 0   0   0 .024 .026 5.7 0    0  
bitvector/modulus_true-unreach-call_true-no-overflow.i 2 .69  .69  28 8.1  0     0     - - - - 2 17    14    340 0   0   2 15     10     370   .62 0  
bitvector/num_conversion_1_true-unreach-call_true-no-overflow.i 2 .14  .14  23 1.2  0     0     - - - - 2 7.0  3.8  280 0   0   2 33     21     560   .68 0  
bitvector/num_conversion_2_true-unreach-call_true-no-overflow.i 2 .17  .17  24 1.3  0     0     - - - - 2 6.9  3.8  290 0   0   0 960     930     2200   .74 0  
bitvector/parity_true-unreach-call_true-no-overflow.i 2 2.8   2.8   30 40    0     0     - - - - 2 29    22    470 0   0   0 960     950     1000   1.9  0  
bitvector/sum02_true-unreach-call_true-no-overflow.i 0 900     900     1500 12000    .016 .070 - - - - 0 .87 .53 41 0   0   0 .034 .035 5.6 0    0  
bitvector/s3_clnt_1_false-unreach-call_true-no-overflow.BV.c.cil.c 0 10     10     230 86    0     0     -32 6.2  3.3  260 0   0   -32 8.9   4.9   330   .62 0   0 5.1  2.8  280 0   0   -32 .76   .76   21    .16  0      - -
bitvector/s3_clnt_2_false-unreach-call_true-no-overflow.BV.c.cil.c 0 8.9   8.9   240 86    0     0     -32 5.9  3.2  290 0   0   -32 9.2   5.5   340   .62 0   0 5.5  3.0  270 0   0   -32 .74   .74   22    .15  0      - -
bitvector/s3_clnt_3_false-unreach-call_true-no-overflow.BV.c.cil.c 0 8.1   8.1   160 68    0     0     -32 6.1  3.3  280 0   0   -32 8.8   4.9   320   .62 0   0 4.8  2.6  260 0   0   -32 .74   .73   21    .15  0      - -
bitvector/s3_clnt_1_true-unreach-call_true-no-overflow.BV.c.cil.c 2 78     78     330 560    0     0     - - - - 2 81    71    880 0   0   2 46     27     800   .71 0  
bitvector/s3_clnt_2_true-unreach-call_true-no-overflow.BV.c.cil.c 2 8.8   8.8   290 93    0     0     - - - - 2 19    11    600 0   0   2 59     33     1000   .75 0  
bitvector/s3_clnt_3_true-unreach-call_true-no-overflow.BV.c.cil.c 2 9.7   9.7   250 88    0     0     - - - - 2 19    11    550 0   0   2 34     19     780   .62 0  
bitvector/s3_srvr_1_alt_true-unreach-call_true-no-overflow.BV.c.cil.c 0 900     900     650 8600    .012 0     - - - - 0 .78 .49 41 0   0   0 .021 .031 5.6 0    0  
bitvector/s3_srvr_1_true-unreach-call_true-no-overflow.BV.c.cil.c 0 900     900     7400 10000    .016 0     - - - - 0 .61 .37 42 0   0   0 .021 .023 5.6 0    0  
bitvector/s3_srvr_2_alt_true-unreach-call_true-no-overflow_false-termination.BV.c.cil.c 0 900     900     6500 11000    .016 0     - - - - 0 .64 .39 41 0   0   0 .022 .022 5.6 0    0  
bitvector/s3_srvr_2_true-unreach-call_true-no-overflow_false-termination.BV.c.cil.c 0 900     900     6600 9900    .012 0     - - - - 0 .61 .37 40 0   0   0 .022 .023 5.6 0    0  
bitvector/s3_srvr_3_alt_true-unreach-call_true-no-overflow.BV.c.cil.c 0 900     900     7100 9800    .016 0     - - - - 0 .74 .45 41 0   0   0 .022 .023 5.7 0    0  
bitvector/s3_srvr_3_true-unreach-call_true-no-overflow.BV.c.cil.c 0 900     900     7000 11000    .016 0     - - - - 0 .59 .37 41 0   0   0 .027 .029 5.8 0    0  
bitvector/soft_float_1_true-unreach-call_true-no-overflow_true-termination.c.cil.c 2 .21  .20  25 1.8  0     0     - - - - 0 900    860    5000 0   0   2 150     130     770   .68 0  
bitvector/soft_float_2_true-unreach-call_true-no-overflow_true-termination.c.cil.c 2 .14  .14  25 1.4  0     0     - - - - 0 830    760    7000 0   0   2 36     23     540   .62 0  
bitvector/soft_float_3_true-unreach-call_true-no-overflow_true-termination.c.cil.c 1 4.0   4.0   160 49    0     0     - - - - 0 900    840    6600 0   0   0 960     890     840   .59 0  
bitvector/soft_float_4_true-unreach-call_true-no-overflow_true-termination.c.cil.c 2 1.2   1.2   25 16    0     0     - - - - 2 91    87    540 0   0   2 330     290     780   .68 0  
bitvector/soft_float_5_true-unreach-call_true-no-overflow_true-termination.c.cil.c 2 .15  .15  25 1.2  0     0     - - - - 0 820    750    7000 0   0   2 25     15     510   .62 0  
bitvector-regression/implicitfloatconversion_false-unreach-call_true-termination.c 1 .12  .11  24 .96 0     0     -32 3.5  1.9  250 0   0   -32 6.5   4.0   290   .62 0   0 3.4  2.0  240 0   0   1 .57   .57   20    .041 0      - -
bitvector-regression/implicitunsignedconversion_false-unreach-call_true-termination.c 1 .12  .11  24 .93 0     0     -32 4.4  2.5  250 0   0   -32 7.1   3.9   300   .62 0   0 3.4  2.0  250 0   0   1 .56   .56   20    .041 0      - -
bitvector-regression/integerpromotion_false-unreach-call_true-termination.c 1 .13  .11  24 .94 0     0     -32 3.6  2.0  250 0   0   -32 6.7   4.2   300   .62 0   0 3.5  2.1  240 0   0   1 .56   .56   20    .041 0      - -
bitvector-regression/recHanoi03_false-unreach-call_true-termination.c 0 .088 .088 24 .97 0     0     0 .65 .40 41 0   0   0 .026 .027 5.6 0    0   0 .99 .65 47 0   0   0 .0013 .0014 .40 0     0      - -
bitvector-regression/signextension2_false-unreach-call_true-termination.c 1 .14  .13  24 .89 0     0     -32 3.7  2.1  250 0   0   -32 6.7   4.2   300   .62 0   0 3.4  2.0  240 0   0   1 .60   .60   20    .045 .0041 - -
bitvector-regression/signextension_false-unreach-call_true-termination.c 1 .12  .11  24 1.0  0     0     -32 4.7  2.6  250 0   0   -32 6.5   3.7   290   .62 0   0 3.4  2.0  250 0   0   1 .59   .59   20    .045 0      - -
bitvector-regression/implicitunsignedconversion_true-unreach-call_true-termination.c 2 .096 .094 24 .82 0     0     - - - - 2 4.2  2.3  250 0   0   2 7.0   4.1   300   .28 0  
bitvector-regression/integerpromotion_true-unreach-call_true-termination.c 2 .11  .11  24 .86 0     0     - - - - 2 3.7  2.1  250 0   0   2 13     7.2   300   .71 0  
bitvector-regression/signextension2_true-unreach-call_true-termination.c 2 .11  .11  23 .84 0     0     - - - - 2 3.6  2.0  250 0   0   2 7.5   4.7   310   .62 0  
bitvector-regression/signextension_true-unreach-call_true-termination.c 2 .10  .099 24 .78 0     0     - - - - 2 4.2  2.3  250 0   0   2 7.3   4.3   310   .62 0  
bitvector-loops/diamond_false-unreach-call2.i 1 .16  .15  24 1.0  0     0     -32 3.9  2.1  260 0   0   1 9.0   5.0   320   .66 0   1 4.0  2.3  250 0   0   1 .60   .60   20    .049 0      - -
bitvector-loops/overflow_false-unreach-call1.i 0 900     900     1200 11000    .016 0     0 .73 .47 41 0   0   0 .020 .021 5.6 0    0   0 .98 .64 47 0   0   0 .0016 .0021 .52 0     0      - -
bitvector-loops/verisec_sendmail__tTflag_arr_one_loop_false-unreach-call_true-termination.i 1 .53  .53  28 7.1  0     0     -32 4.7  2.5  250 0   0   0 97     86     590   .63 0   0 4.2  2.5  260 0   0   1 .61   .61   21    .061 0      - -
sv-benchmarks/c/ status score witness inspect witness cpu (s) wall (s) mem (MB) energy (J) blkio-w (MB) blkio-r (MB) status score witness inspect witness cpu (s) wall (s) mem (MB) energy blkio-w (MB) blkio-r (MB) status score witness inspect witness cpu (s) wall (s) mem (MB) energy blkio-w (MB) blkio-r (MB) status score witness inspect witness cpu (s) wall (s) mem (MB) energy blkio-w (MB) blkio-r (MB) status score witness inspect witness cpu (s) wall (s) mem (MB) energy blkio-w (MB) blkio-r (MB) status score witness inspect witness cpu (s) wall (s) mem (MB) energy blkio-w (MB) blkio-r (MB) status score witness inspect witness cpu (s) wall (s) mem (MB) energy blkio-w (MB) blkio-r (MB)
total 50 53 14000   14000   51000 170000 .24 .070 14 -352 55 30 3000 0   0   14 -254 240 180 4000 6.9 0   14 2 48   28   2900 0   0   14 -88 7.0 7.0 230 .88 .0041 36 38 4100 3800 34000 0   0   36 30 8700 8300 22000 18   0  
    correct results 30 52 110   110   1600 860 0    0     0 2 2 79 58 930 1.3 0   2 2 8.5 4.9 510 0   0   8 8 4.8 4.8 160 .42 .0041 19 38 610 540 7900 0   0   15 30 990 800 8600 9.5 0  
        correct true 22 44 110   110   1400 850 0    0     0 0 0 0 19 38 610 540 7900 0   0   15 30 990 800 8600 9.5 0  
        correct false 8 8 1.7 1.6 200 17 0    0     0 2 2 79 58 930 1.3 0   2 2 8.5 4.9 510 0   0   8 8 4.8 4.8 160 .42 .0041 0 0
    correct-unconfimed results 4 1 31   31   780 290 0    0     0 0 0 0 0 0
        correct-unconfirmed true 1 1 4.0 4.0 160 49 0    0     0 0 0 0 0 0
        correct-unconfirmed false 3 0 27   27   630 240 0    0     0 0 0 0 0 0
    incorrect results 0 11 -352 52 29 2800 0   0   8 -256 60 35 2500 5.0 0   0 3 -96 2.2 2.2 64 .46 0      0 0
        incorrect true 0 11 -352 52 29 2800 0   0   8 -256 60 35 2500 5.0 0   0 3 -96 2.2 2.2 64 .46 0      0 0
        incorrect false 0 0 0 0 0 0 0
score (50 tasks, max score: 86) 53 -352 -254 2 -88 38 30
Run set 2ls.sv-comp19_prop-reachsafety.ReachSafety-BitVectors cpa-seq-validate-violation-witnesses-2ls.sv-comp19_prop-reachsafety.ReachSafety-BitVectors uautomizer-validate-violation-witnesses-2ls.sv-comp19_prop-reachsafety.ReachSafety-BitVectors cpa-witness2test-validate-violation-witnesses-2ls.sv-comp19_prop-reachsafety.ReachSafety-BitVectors fshell-witness2test-validate-violation-witnesses-2ls.sv-comp19_prop-reachsafety.ReachSafety-BitVectors cpa-seq-validate-correctness-witnesses-2ls.sv-comp19_prop-reachsafety.ReachSafety-BitVectors uautomizer-validate-correctness-witnesses-2ls.sv-comp19_prop-reachsafety.ReachSafety-BitVectors