Tool VeriAbs CPAchecker 1.6.1-svn 26773 ULTIMATE Automizer 0.1.23-3204b741 CPA-witness2test 1.6.1-svn 26773 CProver witness2test 0.1 CPAchecker 1.6.1-svn 26773 ULTIMATE Automizer 0.1.23-3204b741
Limits timelimit: 900 s, memlimit: 15000 MB, CPU core limit: 8 timelimit: 90 s, memlimit: 7000 MB, CPU core limit: 2 timelimit: 900 s, memlimit: 7000 MB, CPU core limit: 2
Host apollon* [apollon020; apollon077; apollon078; apollon084; apollon149; apollon164] apollon* [apollon037; apollon065; apollon077; apollon078; apollon155; apollon159] apollon*
OS Linux 4.4.0-101-generic
System CPU: Intel Xeon E3-1230 v5 @ 3.40 GHz, cores: 8, frequency: 3.8 GHz, Turbo Boost: disabled; RAM: 33553 MB CPU: Intel Xeon E3-1230 v5 @ 3.40 GHz, cores: [8; 4], frequency: 3.8 GHz, Turbo Boost: disabled; RAM: [33553 MB; 33554 MB]
Date of execution 2017-12-02 18:04:04 CET 2017-12-03 04:46:33 CET 2017-12-03 06:08:30 CET 2017-12-03 06:21:09 CET 2017-12-03 06:27:12 CET 2017-12-03 03:55:53 CET 2017-12-03 04:55:47 CET
Run set veriabs.sv-comp18.ReachSafety-BitVectors cpa-seq-validate-violation-witnesses-veriabs.sv-comp18-violation-witness.ReachSafety-BitVectors uautomizer-validate-violation-witnesses-veriabs.sv-comp18-violation-witness.ReachSafety-BitVectors cpa-witness2test-validate-violation-witnesses-veriabs.sv-comp18-violation-witness.ReachSafety-BitVectors fshell-witness2test-validate-violation-witnesses-veriabs.sv-comp18-violation-witness.ReachSafety-BitVectors cpa-seq-validate-correctness-witnesses-veriabs.sv-comp18-correctness-witness.ReachSafety-BitVectors uautomizer-validate-correctness-witnesses-veriabs.sv-comp18-correctness-witness.ReachSafety-BitVectors
Options -witnessValidation -setprop witness.checkProgramHash=false -heap 5000m -benchmark -witness ../../results-verified/veriabs.2017-12-02_1804.logfiles/sv-comp18.${inputfile_name}.files/witness.graphml -setprop cpa.predicate.memoryAllocationsAlwaysSucceed=true -setprop cpa.smg.memoryAllocationFunctions=malloc,__kmalloc,kmalloc,kzalloc,kzalloc_node,ldv_zalloc,ldv_malloc -setprop cpa.smg.arrayAllocationFunctions=calloc,kmalloc_array,kcalloc -setprop cpa.smg.zeroingMemoryAllocation=calloc,kzalloc,kcalloc,kzalloc_node,ldv_zalloc -setprop cpa.smg.deallocationFunctions=free,kfree,kfree_const --full-output --validate ../../results-verified/veriabs.2017-12-02_1804.logfiles/sv-comp18.${inputfile_name}.files/witness.graphml -witness2test -setprop witness.checkProgramHash=false -heap 5000m -benchmark -witness ../../results-verified/veriabs.2017-12-02_1804.logfiles/sv-comp18.${inputfile_name}.files/witness.graphml -setprop analysis.summaryEdges=true -setprop cpa.callstack.skipVoidRecursion=true -setprop cpa.callstack.skipFunctionPointerRecursion=true --graphml-witness ../../results-verified/veriabs.2017-12-02_1804.logfiles/sv-comp18.${inputfile_name}.files/witness.graphml -witnessValidation -setprop witness.checkProgramHash=false -heap 5000m -benchmark -witness ../../results-verified/veriabs.2017-12-02_1804.logfiles/sv-comp18.${inputfile_name}.files/witness.graphml -setprop cpa.predicate.memoryAllocationsAlwaysSucceed=true --full-output --validate ../../results-verified/veriabs.2017-12-02_1804.logfiles/sv-comp18.${inputfile_name}.files/witness.graphml
sv-benchmarks/c/ status score witness inspect witness cpu (s) mem (MB) energy (J) status score witness inspect witness cpu (s) mem (MB) energy status score witness inspect witness cpu (s) mem (MB) energy status score witness inspect witness cpu (s) mem (MB) energy status score witness inspect witness cpu (s) mem (MB) energy status score witness inspect witness cpu (s) mem (MB) energy status score witness inspect witness cpu (s) mem (MB) energy
bitvector/byte_add_false-unreach-call_true-no-overflow_true-termination.i 1 29   430 260 1 3.8  270 1 36     600   0 3.4  210 1 .71   19    - -
bitvector/sum02_false-unreach-call_true-no-overflow.i 0 470   3100 3700 0 .40 44 0 .019 4.9 0 .68 51 0 .0013 .26 - -
bitvector/byte_add_1_true-unreach-call_true-no-overflow_true-termination.i 2 29   570 210 - - - - 2 14    320 0 960     2700  
bitvector/byte_add_2_true-unreach-call_true-no-overflow_true-termination.i 2 27   480 180 - - - - 2 12    320 0 960     2700  
bitvector/gcd_1_true-unreach-call_true-no-overflow.i 2 21   300 190 - - - - 2 12    320 -16 6.1   270  
bitvector/gcd_2_true-unreach-call_true-no-overflow.i 2 53   400 590 - - - - 2 140    480 0 960     790  
bitvector/gcd_3_true-unreach-call_true-no-overflow.i 2 52   410 630 - - - - 2 140    460 0 550     900  
bitvector/gcd_4_true-unreach-call_true-no-overflow_true-termination.i 2 17   320 120 - - - - 2 8.2  320 -16 5.7   260  
bitvector/interleave_bits_true-unreach-call_true-no-overflow.i 2 18   330 120 - - - - 2 8.2  370 2 380     1000  
bitvector/jain_1_true-unreach-call_true-no-overflow_false-termination.i 0 370   4800 4000 - - - - 0 .57 46 0 .019 4.8
bitvector/jain_2_true-unreach-call_true-no-overflow_false-termination.i 0 510   4300 6100 - - - - 0 .67 43 0 .018 4.8
bitvector/jain_4_true-unreach-call_true-no-overflow_false-termination.i 0 620   5700 6900 - - - - 0 .57 41 0 .018 5.0
bitvector/jain_5_true-unreach-call_true-no-overflow.i 1 8.0 220 63 - - - - 0 900    1700 0 960     640  
bitvector/jain_6_true-unreach-call_true-no-overflow_false-termination.i 0 620   5400 6600 - - - - 0 .57 43 0 .020 4.9
bitvector/jain_7_true-unreach-call_true-no-overflow_false-termination.i 0 510   5100 6800 - - - - 0 .41 43 0 .020 4.9
bitvector/modulus_true-unreach-call_true-no-overflow.i 2 30   610 290 - - - - 2 16    340 2 13     310  
bitvector/num_conversion_1_true-unreach-call_true-no-overflow.i 2 16   290 110 - - - - 2 4.9  270 2 59     640  
bitvector/num_conversion_2_true-unreach-call_true-no-overflow.i 2 16   310 140 - - - - 2 5.2  280 0 960     1100  
bitvector/parity_true-unreach-call_true-no-overflow.i 2 32   340 330 - - - - 2 25    410 0 960     1000  
bitvector/sum02_true-unreach-call_true-no-overflow.i 0 390   3200 3100 - - - - 0 .54 43 0 .018 4.9
bitvector/s3_clnt_1_false-unreach-call_true-no-overflow.BV.c.cil.c 1 59   420 590 1 5.5  280 1 20     490   0 3.1  220 1 .74   21    - -
bitvector/s3_clnt_2_false-unreach-call_true-no-overflow.BV.c.cil.c 1 150   880 1700 1 6.0  290 1 20     520   0 4.4  220 1 .74   21    - -
bitvector/s3_clnt_3_false-unreach-call_true-no-overflow.BV.c.cil.c 1 130   790 1400 1 3.7  300 1 17     430   0 3.1  220 -32 .73   20    - -
bitvector/s3_clnt_1_true-unreach-call_true-no-overflow.BV.c.cil.c 2 93   750 900 - - - - 2 30    560 2 200     2300  
bitvector/s3_clnt_2_true-unreach-call_true-no-overflow.BV.c.cil.c 1 170   900 1800 - - - - 0 7.8  350 -16 8.6   330  
bitvector/s3_clnt_3_true-unreach-call_true-no-overflow.BV.c.cil.c 1 160   790 1700 - - - - 0 7.1  290 -16 11     360  
bitvector/s3_srvr_1_alt_true-unreach-call_true-no-overflow.BV.c.cil.c 0 550   1000 6400 - - - - 0 .53 42 0 .019 5.0
bitvector/s3_srvr_1_true-unreach-call_true-no-overflow.BV.c.cil.c 0 900   1300 5000 - - - - 0 .73 41 0 .020 4.9
bitvector/s3_srvr_2_alt_true-unreach-call_true-no-overflow_false-termination.BV.c.cil.c 0 900   1400 7400 - - - - 0 .60 41 0 .018 4.9
bitvector/s3_srvr_2_true-unreach-call_true-no-overflow_false-termination.BV.c.cil.c 0 900   1400 7500 - - - - 0 .64 41 0 .018 4.9
bitvector/s3_srvr_3_alt_true-unreach-call_true-no-overflow.BV.c.cil.c 0 900   1300 5600 - - - - 0 .73 42 0 .018 5.0
bitvector/s3_srvr_3_true-unreach-call_true-no-overflow.BV.c.cil.c 0 900   1200 5800 - - - - 0 .65 41 0 .019 4.9
bitvector/soft_float_1_true-unreach-call_true-no-overflow_true-termination.c.cil.c 2 98   820 960 - - - - 0 900    6100 2 120     770  
bitvector/soft_float_2_true-unreach-call_true-no-overflow_true-termination.c.cil.c 1 40   780 420 - - - - 0 900    4600 0 960     670  
bitvector/soft_float_3_true-unreach-call_true-no-overflow_true-termination.c.cil.c 1 85   740 850 - - - - 0 920    6300 0 960     750  
bitvector/soft_float_4_true-unreach-call_true-no-overflow_true-termination.c.cil.c 2 100   810 1100 - - - - 2 210    630 2 300     810  
bitvector/soft_float_5_true-unreach-call_true-no-overflow_true-termination.c.cil.c 1 40   740 390 - - - - 0 900    4600 0 960     680  
bitvector-regression/implicitfloatconversion_false-unreach-call_true-termination.c 1 7.5 300 63 1 3.2  260 1 9.2   220   0 2.0  210 1 .57   18    - -
bitvector-regression/implicitunsignedconversion_false-unreach-call_true-termination.c 1 7.6 300 61 1 2.1  260 1 4.9   210   0 2.7  210 1 .56   18    - -
bitvector-regression/integerpromotion_false-unreach-call_true-termination.c 1 7.3 270 62 1 3.2  260 1 6.2   220   0 2.8  210 1 .60   18    - -
bitvector-regression/recHanoi03_false-unreach-call_true-termination.c 0 7.1 160 57 0 .53 41 0 .024 4.8 0 .63 49 0 .0012 .26 - -
bitvector-regression/signextension2_false-unreach-call_true-termination.c 1 7.7 300 61 1 2.0  260 -32 4.6   210   0 2.9  210 1 .67   18    - -
bitvector-regression/signextension_false-unreach-call_true-termination.c 1 7.2 280 61 1 2.1  260 -32 4.6   210   0 2.0  210 1 .56   18    - -
bitvector-regression/implicitunsignedconversion_true-unreach-call_true-termination.c 2 7.7 270 71 - - - - 2 3.9  250 2 4.6   250  
bitvector-regression/integerpromotion_true-unreach-call_true-termination.c 2 7.8 260 67 - - - - 2 3.7  250 2 8.8   230  
bitvector-regression/signextension2_true-unreach-call_true-termination.c 2 8.1 270 69 - - - - 2 3.0  240 2 3.5   260  
bitvector-regression/signextension_true-unreach-call_true-termination.c 2 8.0 260 71 - - - - 2 3.2  250 2 3.6   260  
bitvector-loops/diamond_false-unreach-call2.i 1 23   430 190 -32 3.8  260 1 6.0   260   0 2.8  210 1 .61   18    - -
bitvector-loops/overflow_false-unreach-call1.i 1 11   280 84 0 91    1600 -32 4.6   220   0 2.7  180 1 4.3    18    - -
bitvector-loops/verisec_sendmail__tTflag_arr_one_loop_false-unreach-call_true-termination.i 0 19   280 160 -32 2.8  270 0 59     7000   0 3.4  220 0 .62   19    - -
sv-benchmarks/c/ status score witness inspect witness cpu (s) mem (MB) energy (J) status score witness inspect witness cpu (s) mem (MB) energy status score witness inspect witness cpu (s) mem (MB) energy status score witness inspect witness cpu (s) mem (MB) energy status score witness inspect witness cpu (s) mem (MB) energy status score witness inspect witness cpu (s) mem (MB) energy status score witness inspect witness cpu (s) mem (MB) energy
total 50 53 10000 56000 91000 14 -55 130   4600 14 -88 190 11000 14 0 37 2600 14 -22 11    230 36 34 5200 30000 36 -44 10000 20000
    correct results 29 47 1100 13000 11000 9 9 32   2400 8 8 120 3000 0 10 10 10    190 17 34 640 6100 10 20 1100 6900
        correct true 18 36 640 7800 6200 0 0 0 0 17 34 640 6100 10 20 1100 6900
        correct false 11 11 440 4700 4500 9 9 32   2400 8 8 120 3000 0 10 10 10    190 0 0
    correct-unconfimed results 7 6 530 4400 5300 0 0 0 0 0 0
        correct-unconfirmed true 6 6 510 4200 5200 0 0 0 0 0 0
        correct-unconfirmed false 1 0 19 280 160 0 0 0 0 0 0
    incorrect results 0 2 -64 6.6 520 3 -96 14 640 0 1 -32 .73 20 0 4 -64 32 1200
        incorrect true 0 2 -64 6.6 520 3 -96 14 640 0 1 -32 .73 20 0 0
        incorrect false 0 0 0 0 0 0 4 -64 32 1200
score (50 tasks, max score: 86) 53 -55 -88 0 -22 34 -44
Run set veriabs.sv-comp18.ReachSafety-BitVectors cpa-seq-validate-violation-witnesses-veriabs.sv-comp18-violation-witness.ReachSafety-BitVectors uautomizer-validate-violation-witnesses-veriabs.sv-comp18-violation-witness.ReachSafety-BitVectors cpa-witness2test-validate-violation-witnesses-veriabs.sv-comp18-violation-witness.ReachSafety-BitVectors fshell-witness2test-validate-violation-witnesses-veriabs.sv-comp18-violation-witness.ReachSafety-BitVectors cpa-seq-validate-correctness-witnesses-veriabs.sv-comp18-correctness-witness.ReachSafety-BitVectors uautomizer-validate-correctness-witnesses-veriabs.sv-comp18-correctness-witness.ReachSafety-BitVectors