Tool ULTIMATE Taipan 0.1.23-3204b741 CPAchecker 1.6.1-svn 26773 ULTIMATE Automizer 0.1.23-3204b741 CPA-witness2test 1.6.1-svn 26773 CProver witness2test 0.1 CPAchecker 1.6.1-svn 26773 ULTIMATE Automizer 0.1.23-3204b741
Limits timelimit: 900 s, memlimit: 15000 MB, CPU core limit: 8 timelimit: 90 s, memlimit: 7000 MB, CPU core limit: 2 timelimit: 900 s, memlimit: 7000 MB, CPU core limit: 2
Host apollon*
OS Linux 4.4.0-101-generic
System CPU: Intel Xeon E3-1230 v5 @ 3.40 GHz, cores: 8, frequency: 3.8 GHz, Turbo Boost: disabled; RAM: 33553 MB CPU: Intel Xeon E3-1230 v5 @ 3.40 GHz, cores: [8; 4], frequency: 3.8 GHz, Turbo Boost: disabled; RAM: [33553 MB; 33554 MB]
Date of execution 2017-12-02 17:23:13 CET 2017-12-03 07:22:17 CET 2017-12-03 07:45:29 CET 2017-12-03 07:47:53 CET 2017-12-03 07:50:34 CET 2017-12-03 06:47:45 CET 2017-12-03 07:25:40 CET
Run set utaipan.sv-comp18.ReachSafety-BitVectors cpa-seq-validate-violation-witnesses-utaipan.sv-comp18-violation-witness.ReachSafety-BitVectors uautomizer-validate-violation-witnesses-utaipan.sv-comp18-violation-witness.ReachSafety-BitVectors cpa-witness2test-validate-violation-witnesses-utaipan.sv-comp18-violation-witness.ReachSafety-BitVectors fshell-witness2test-validate-violation-witnesses-utaipan.sv-comp18-violation-witness.ReachSafety-BitVectors cpa-seq-validate-correctness-witnesses-utaipan.sv-comp18-correctness-witness.ReachSafety-BitVectors uautomizer-validate-correctness-witnesses-utaipan.sv-comp18-correctness-witness.ReachSafety-BitVectors
Options --full-output -witnessValidation -setprop witness.checkProgramHash=false -heap 5000m -benchmark -witness ../../results-verified/utaipan.2017-12-02_1723.logfiles/sv-comp18.${inputfile_name}.files/witness.graphml -setprop cpa.predicate.memoryAllocationsAlwaysSucceed=true -setprop cpa.smg.memoryAllocationFunctions=malloc,__kmalloc,kmalloc,kzalloc,kzalloc_node,ldv_zalloc,ldv_malloc -setprop cpa.smg.arrayAllocationFunctions=calloc,kmalloc_array,kcalloc -setprop cpa.smg.zeroingMemoryAllocation=calloc,kzalloc,kcalloc,kzalloc_node,ldv_zalloc -setprop cpa.smg.deallocationFunctions=free,kfree,kfree_const --full-output --validate ../../results-verified/utaipan.2017-12-02_1723.logfiles/sv-comp18.${inputfile_name}.files/witness.graphml -witness2test -setprop witness.checkProgramHash=false -heap 5000m -benchmark -witness ../../results-verified/utaipan.2017-12-02_1723.logfiles/sv-comp18.${inputfile_name}.files/witness.graphml -setprop analysis.summaryEdges=true -setprop cpa.callstack.skipVoidRecursion=true -setprop cpa.callstack.skipFunctionPointerRecursion=true --graphml-witness ../../results-verified/utaipan.2017-12-02_1723.logfiles/sv-comp18.${inputfile_name}.files/witness.graphml -witnessValidation -setprop witness.checkProgramHash=false -heap 5000m -benchmark -witness ../../results-verified/utaipan.2017-12-02_1723.logfiles/sv-comp18.${inputfile_name}.files/witness.graphml -setprop cpa.predicate.memoryAllocationsAlwaysSucceed=true --full-output --validate ../../results-verified/utaipan.2017-12-02_1723.logfiles/sv-comp18.${inputfile_name}.files/witness.graphml
sv-benchmarks/c/ status score witness inspect witness cpu (s) mem (MB) energy (J) status score witness inspect witness cpu (s) mem (MB) energy status score witness inspect witness cpu (s) mem (MB) energy status score witness inspect witness cpu (s) mem (MB) energy status score witness inspect witness cpu (s) mem (MB) energy status score witness inspect witness cpu (s) mem (MB) energy status score witness inspect witness cpu (s) mem (MB) energy
bitvector/byte_add_false-unreach-call_true-no-overflow_true-termination.i 1 110   1500 940 1 3.6  280 1 25     510   0 3.8  220 -32 .61   19    - -
bitvector/sum02_false-unreach-call_true-no-overflow.i 0 900   700 11000 0 .56 42 0 .050 5.0 0 .80 47 0 .0037 .34 - -
bitvector/byte_add_1_true-unreach-call_true-no-overflow_true-termination.i 0 900   2600 12000 - - - - 0 .56 41 0 .017 5.0
bitvector/byte_add_2_true-unreach-call_true-no-overflow_true-termination.i 0 900   3100 12000 - - - - 0 .55 43 0 .019 4.9
bitvector/gcd_1_true-unreach-call_true-no-overflow.i 0 900   1000 12000 - - - - 0 .67 41 0 .018 4.9
bitvector/gcd_2_true-unreach-call_true-no-overflow.i 0 900   1100 11000 - - - - 0 .52 44 0 .043 4.9
bitvector/gcd_3_true-unreach-call_true-no-overflow.i 0 510   1200 4100 - - - - 0 .53 41 0 .048 4.9
bitvector/gcd_4_true-unreach-call_true-no-overflow_true-termination.i 2 240   900 2800 - - - - 2 5.8  300 2 46     590  
bitvector/interleave_bits_true-unreach-call_true-no-overflow.i 2 230   1800 3100 - - - - 2 6.1  310 2 120     650  
bitvector/jain_1_true-unreach-call_true-no-overflow_false-termination.i 2 4.6 290 39 - - - - 2 4.6  270 2 5.5   260  
bitvector/jain_2_true-unreach-call_true-no-overflow_false-termination.i 2 4.7 290 40 - - - - 2 4.0  280 2 11     280  
bitvector/jain_4_true-unreach-call_true-no-overflow_false-termination.i 2 4.8 290 44 - - - - 2 4.2  280 2 5.2   260  
bitvector/jain_5_true-unreach-call_true-no-overflow.i 1 6.3 310 53 - - - - 0 630    7000 0 960     710  
bitvector/jain_6_true-unreach-call_true-no-overflow_false-termination.i 2 8.0 300 86 - - - - 2 4.9  290 2 6.6   280  
bitvector/jain_7_true-unreach-call_true-no-overflow_false-termination.i 2 5.1 290 44 - - - - 0 900    510 2 40     300  
bitvector/modulus_true-unreach-call_true-no-overflow.i 2 13   500 110 - - - - 2 11    320 2 12     300  
bitvector/num_conversion_1_true-unreach-call_true-no-overflow.i 2 59   670 670 - - - - 2 5.0  270 2 51     590  
bitvector/num_conversion_2_true-unreach-call_true-no-overflow.i 0 900   1300 12000 - - - - 0 .51 41 0 .050 5.0
bitvector/parity_true-unreach-call_true-no-overflow.i 0 900   1000 12000 - - - - 0 .58 43 0 .021 4.8
bitvector/sum02_true-unreach-call_true-no-overflow.i 0 900   650 11000 - - - - 0 .53 42 0 .026 4.9
bitvector/s3_clnt_1_false-unreach-call_true-no-overflow.BV.c.cil.c 1 26   580 210 -32 6.0  270 1 15     450   0 4.1  220 -32 .64   20    - -
bitvector/s3_clnt_2_false-unreach-call_true-no-overflow.BV.c.cil.c 1 27   690 210 -32 6.0  270 1 20     520   0 4.3  220 -32 .64   20    - -
bitvector/s3_clnt_3_false-unreach-call_true-no-overflow.BV.c.cil.c 1 24   610 190 -32 6.0  270 1 17     410   0 3.7  220 -32 .63   20    - -
bitvector/s3_clnt_1_true-unreach-call_true-no-overflow.BV.c.cil.c 2 39   1100 330 - - - - 2 72    810 2 41     760  
bitvector/s3_clnt_2_true-unreach-call_true-no-overflow.BV.c.cil.c 2 45   1400 360 - - - - 2 21    560 2 42     920  
bitvector/s3_clnt_3_true-unreach-call_true-no-overflow.BV.c.cil.c 2 270   4800 3700 - - - - 2 14    410 0 120     7000  
bitvector/s3_srvr_1_alt_true-unreach-call_true-no-overflow.BV.c.cil.c 0 900   5100 12000 - - - - 0 .54 44 0 .019 4.9
bitvector/s3_srvr_1_true-unreach-call_true-no-overflow.BV.c.cil.c 2 230   4700 2500 - - - - 0 900    4400 2 47     1000  
bitvector/s3_srvr_2_alt_true-unreach-call_true-no-overflow_false-termination.BV.c.cil.c 0 900   5400 14000 - - - - 0 .63 43 0 .020 4.9
bitvector/s3_srvr_2_true-unreach-call_true-no-overflow_false-termination.BV.c.cil.c 0 900   5000 12000 - - - - 0 .71 44 0 .047 4.8
bitvector/s3_srvr_3_alt_true-unreach-call_true-no-overflow.BV.c.cil.c 2 250   4800 2900 - - - - 0 910    5300 2 33     970  
bitvector/s3_srvr_3_true-unreach-call_true-no-overflow.BV.c.cil.c 2 230   4800 2800 - - - - 0 900    5400 2 35     870  
bitvector/soft_float_1_true-unreach-call_true-no-overflow_true-termination.c.cil.c 0 110   870 1400 - - - - 0 .64 42 0 .021 4.9
bitvector/soft_float_2_true-unreach-call_true-no-overflow_true-termination.c.cil.c 2 84   1300 830 - - - - 0 900    6100 2 51     690  
bitvector/soft_float_3_true-unreach-call_true-no-overflow_true-termination.c.cil.c 0 900   1100 10000 - - - - 0 .54 42 0 .018 4.9
bitvector/soft_float_4_true-unreach-call_true-no-overflow_true-termination.c.cil.c 2 860   940 11000 - - - - 2 250    630 2 310     840  
bitvector/soft_float_5_true-unreach-call_true-no-overflow_true-termination.c.cil.c 2 63   1200 620 - - - - 0 900    6100 2 22     590  
bitvector-regression/implicitfloatconversion_false-unreach-call_true-termination.c 1 8.3 240 67 1 2.9  260 1 8.3   230   0 2.6  180 1 .59   18    - -
bitvector-regression/implicitunsignedconversion_false-unreach-call_true-termination.c 1 4.0 240 37 1 3.1  250 1 4.3   220   0 2.6  180 1 .59   18    - -
bitvector-regression/integerpromotion_false-unreach-call_true-termination.c 1 9.6 320 76 1 2.9  260 1 8.3   220   0 2.5  180 1 .56   18    - -
bitvector-regression/recHanoi03_false-unreach-call_true-termination.c 1 290   1200 4000 1 5.3  280 -32 4.9   270   0 3.6  210 -32 .60   19    - -
bitvector-regression/signextension2_false-unreach-call_true-termination.c 1 4.4 250 34 1 2.9  260 1 4.4   220   0 2.8  190 1 .59   18    - -
bitvector-regression/signextension_false-unreach-call_true-termination.c 1 4.1 250 34 1 2.9  260 1 5.0   230   0 2.6  180 1 .60   18    - -
bitvector-regression/implicitunsignedconversion_true-unreach-call_true-termination.c 2 4.3 270 37 - - - - 2 2.8  260 2 4.6   250  
bitvector-regression/integerpromotion_true-unreach-call_true-termination.c 2 8.9 290 70 - - - - 2 3.1  240 2 8.6   250  
bitvector-regression/signextension2_true-unreach-call_true-termination.c 2 4.7 290 39 - - - - 2 3.8  260 2 5.3   250  
bitvector-regression/signextension_true-unreach-call_true-termination.c 2 4.7 290 41 - - - - 2 3.0  240 2 5.3   260  
bitvector-loops/diamond_false-unreach-call2.i 1 13   550 110 1 3.1  260 1 5.7   280   0 3.0  210 -32 .60   19    - -
bitvector-loops/overflow_false-unreach-call1.i 0 900   1500 9700 0 .55 43 0 .043 4.9 0 .81 49 0 .0037 .34 - -
bitvector-loops/verisec_sendmail__tTflag_arr_one_loop_false-unreach-call_true-termination.i 0 550   2000 8400 -32 3.4  260 0 57     7000   0 3.0  190 -32 .58   19    - -
sv-benchmarks/c/ status score witness inspect witness cpu (s) mem (MB) energy (J) status score witness inspect witness cpu (s) mem (MB) energy status score witness inspect witness cpu (s) mem (MB) energy status score witness inspect witness cpu (s) mem (MB) energy status score witness inspect witness cpu (s) mem (MB) energy status score witness inspect witness cpu (s) mem (MB) energy status score witness inspect witness cpu (s) mem (MB) energy
total 50 56 16000   72000 200000 14 -120 49 3300 14 -22 180   11000 14 0 40 2500 14 -219 7.2 230 36 32 6500 41000 36 42 2000 19000
    correct results 33 55 3200   38000 38000 8 8 27 2100 10 10 110   3300 0 5 5 2.9 92 16 32 410 5700 21 42 900 11000
        correct true 22 44 2700   31000 32000 0 0 0 0 16 32 410 5700 21 42 900 11000
        correct false 11 11 520   6400 6000 8 8 27 2100 10 10 110   3300 0 5 5 2.9 92 0 0
    correct-unconfimed results 2 1 560   2300 8500 0 0 0 0 0 0
        correct-unconfirmed true 1 1 6.3 310 53 0 0 0 0 0 0
        correct-unconfirmed false 1 0 550   2000 8400 0 0 0 0 0 0
    incorrect results 0 4 -128 21 1100 1 -32 4.9 270 0 7 -224 4.3 140 0 0
        incorrect true 0 4 -128 21 1100 1 -32 4.9 270 0 7 -224 4.3 140 0 0
        incorrect false 0 0 0 0 0 0 0
score (50 tasks, max score: 86) 56 -120 -22 0 -219 32 42
Run set utaipan.sv-comp18.ReachSafety-BitVectors cpa-seq-validate-violation-witnesses-utaipan.sv-comp18-violation-witness.ReachSafety-BitVectors uautomizer-validate-violation-witnesses-utaipan.sv-comp18-violation-witness.ReachSafety-BitVectors cpa-witness2test-validate-violation-witnesses-utaipan.sv-comp18-violation-witness.ReachSafety-BitVectors fshell-witness2test-validate-violation-witnesses-utaipan.sv-comp18-violation-witness.ReachSafety-BitVectors cpa-seq-validate-correctness-witnesses-utaipan.sv-comp18-correctness-witness.ReachSafety-BitVectors uautomizer-validate-correctness-witnesses-utaipan.sv-comp18-correctness-witness.ReachSafety-BitVectors