Tool ULTIMATE Kojak 0.1.23-3204b741 CPAchecker 1.6.1-svn 26773 ULTIMATE Automizer 0.1.23-3204b741 CPA-witness2test 1.6.1-svn 26773 CProver witness2test 0.1 CPAchecker 1.6.1-svn 26773 ULTIMATE Automizer 0.1.23-3204b741
Limits timelimit: 900 s, memlimit: 15000 MB, CPU core limit: 8 timelimit: 90 s, memlimit: 7000 MB, CPU core limit: 2 timelimit: 900 s, memlimit: 7000 MB, CPU core limit: 2
Host apollon*
OS Linux 4.4.0-101-generic
System CPU: Intel Xeon E3-1230 v5 @ 3.40 GHz, cores: 8, frequency: 3.8 GHz, Turbo Boost: disabled; RAM: 33553 MB CPU: Intel Xeon E3-1230 v5 @ 3.40 GHz, cores: [8; 4], frequency: 3.8 GHz, Turbo Boost: disabled; RAM: [33553 MB; 33554 MB] CPU: Intel Xeon E3-1230 v5 @ 3.40 GHz, cores: 8, frequency: 3.8 GHz, Turbo Boost: disabled; RAM: 33553 MB CPU: Intel Xeon E3-1230 v5 @ 3.40 GHz, cores: [8; 4], frequency: 3.8 GHz, Turbo Boost: disabled; RAM: [33553 MB; 33554 MB]
Date of execution 2017-12-02 02:33:02 CET 2017-12-03 03:22:18 CET 2017-12-03 03:55:21 CET 2017-12-03 04:22:06 CET 2017-12-03 04:36:43 CET 2017-12-03 00:36:56 CET 2017-12-03 03:32:10 CET
Run set ukojak.sv-comp18.ReachSafety-BitVectors cpa-seq-validate-violation-witnesses-ukojak.sv-comp18-violation-witness.ReachSafety-BitVectors uautomizer-validate-violation-witnesses-ukojak.sv-comp18-violation-witness.ReachSafety-BitVectors cpa-witness2test-validate-violation-witnesses-ukojak.sv-comp18-violation-witness.ReachSafety-BitVectors fshell-witness2test-validate-violation-witnesses-ukojak.sv-comp18-violation-witness.ReachSafety-BitVectors cpa-seq-validate-correctness-witnesses-ukojak.sv-comp18-correctness-witness.ReachSafety-BitVectors uautomizer-validate-correctness-witnesses-ukojak.sv-comp18-correctness-witness.ReachSafety-BitVectors
Options --full-output -witnessValidation -setprop witness.checkProgramHash=false -heap 5000m -benchmark -witness ../../results-verified/ukojak.2017-12-02_0233.logfiles/sv-comp18.${inputfile_name}.files/witness.graphml -setprop cpa.predicate.memoryAllocationsAlwaysSucceed=true -setprop cpa.smg.memoryAllocationFunctions=malloc,__kmalloc,kmalloc,kzalloc,kzalloc_node,ldv_zalloc,ldv_malloc -setprop cpa.smg.arrayAllocationFunctions=calloc,kmalloc_array,kcalloc -setprop cpa.smg.zeroingMemoryAllocation=calloc,kzalloc,kcalloc,kzalloc_node,ldv_zalloc -setprop cpa.smg.deallocationFunctions=free,kfree,kfree_const --full-output --validate ../../results-verified/ukojak.2017-12-02_0233.logfiles/sv-comp18.${inputfile_name}.files/witness.graphml -witness2test -setprop witness.checkProgramHash=false -heap 5000m -benchmark -witness ../../results-verified/ukojak.2017-12-02_0233.logfiles/sv-comp18.${inputfile_name}.files/witness.graphml -setprop analysis.summaryEdges=true -setprop cpa.callstack.skipVoidRecursion=true -setprop cpa.callstack.skipFunctionPointerRecursion=true --graphml-witness ../../results-verified/ukojak.2017-12-02_0233.logfiles/sv-comp18.${inputfile_name}.files/witness.graphml -witnessValidation -setprop witness.checkProgramHash=false -heap 5000m -benchmark -witness ../../results-verified/ukojak.2017-12-02_0233.logfiles/sv-comp18.${inputfile_name}.files/witness.graphml -setprop cpa.predicate.memoryAllocationsAlwaysSucceed=true --full-output --validate ../../results-verified/ukojak.2017-12-02_0233.logfiles/sv-comp18.${inputfile_name}.files/witness.graphml
sv-benchmarks/c/ status score witness inspect witness cpu (s) mem (MB) energy (J) status score witness inspect witness cpu (s) mem (MB) energy status score witness inspect witness cpu (s) mem (MB) energy status score witness inspect witness cpu (s) mem (MB) energy status score witness inspect witness cpu (s) mem (MB) energy status score witness inspect witness cpu (s) mem (MB) energy status score witness inspect witness cpu (s) mem (MB) energy
bitvector/byte_add_false-unreach-call_true-no-overflow_true-termination.i 1 31   490 280 1 3.8  270 1 36     590   0 5.2  220 -32 .61   19    - -
bitvector/sum02_false-unreach-call_true-no-overflow.i 0 900   680 10000 0 .54 43 0 .019 4.9 0 .90 50 0 .0018 .29 - -
bitvector/byte_add_1_true-unreach-call_true-no-overflow_true-termination.i 2 720   1600 7700 - - - - 2 11    300 0 960     1100  
bitvector/byte_add_2_true-unreach-call_true-no-overflow_true-termination.i 0 900   1500 7600 - - - - 0 .55 41 0 .028 4.8
bitvector/gcd_1_true-unreach-call_true-no-overflow.i 0 660   670 4700 - - - - 0 .67 42 0 .024 4.9
bitvector/gcd_2_true-unreach-call_true-no-overflow.i 0 900   520 11000 - - - - 0 .68 43 0 .019 4.9
bitvector/gcd_3_true-unreach-call_true-no-overflow.i 0 900   500 12000 - - - - 0 .62 44 0 .022 5.0
bitvector/gcd_4_true-unreach-call_true-no-overflow_true-termination.i 2 11   580 97 - - - - 2 5.2  300 2 46     580  
bitvector/interleave_bits_true-unreach-call_true-no-overflow.i 2 100   2600 1100 - - - - 2 6.5  310 2 130     680  
bitvector/jain_1_true-unreach-call_true-no-overflow_false-termination.i 0 900   1700 12000 - - - - 0 .57 41 0 .018 5.0
bitvector/jain_2_true-unreach-call_true-no-overflow_false-termination.i 2 16   330 170 - - - - 2 4.9  280 2 21     300  
bitvector/jain_4_true-unreach-call_true-no-overflow_false-termination.i 2 6.2 320 50 - - - - 2 5.6  280 2 6.3   270  
bitvector/jain_5_true-unreach-call_true-no-overflow.i 0 900   5200 13000 - - - - 0 .40 43 0 .020 4.9
bitvector/jain_6_true-unreach-call_true-no-overflow_false-termination.i 0 900   2100 10000 - - - - 0 .53 41 0 .018 4.8
bitvector/jain_7_true-unreach-call_true-no-overflow_false-termination.i 0 900   2900 13000 - - - - 0 .53 43 0 .019 4.9
bitvector/modulus_true-unreach-call_true-no-overflow.i 2 110   660 1500 - - - - 2 14    320 2 9.4   280  
bitvector/num_conversion_1_true-unreach-call_true-no-overflow.i 2 120   470 1700 - - - - 2 5.3  290 2 52     640  
bitvector/num_conversion_2_true-unreach-call_true-no-overflow.i 2 240   780 2900 - - - - 2 6.5  280 0 960     1100  
bitvector/parity_true-unreach-call_true-no-overflow.i 0 900   720 13000 - - - - 0 .56 45 0 .018 4.9
bitvector/sum02_true-unreach-call_true-no-overflow.i 0 900   740 11000 - - - - 0 .53 43 0 .019 4.9
bitvector/s3_clnt_1_false-unreach-call_true-no-overflow.BV.c.cil.c 0 900   6300 13000 0 .62 41 0 .018 4.8 0 1.1  49 0 .0016 .26 - -
bitvector/s3_clnt_2_false-unreach-call_true-no-overflow.BV.c.cil.c 0 900   6200 13000 0 .56 43 0 .018 4.8 0 .93 50 0 .0015 .34 - -
bitvector/s3_clnt_3_false-unreach-call_true-no-overflow.BV.c.cil.c 1 88   1000 1100 -32 6.8  280 1 17     410   0 4.5  220 -32 .76   20    - -
bitvector/s3_clnt_1_true-unreach-call_true-no-overflow.BV.c.cil.c 0 900   6300 11000 - - - - 0 .60 43 0 .019 4.8
bitvector/s3_clnt_2_true-unreach-call_true-no-overflow.BV.c.cil.c 0 900   6300 12000 - - - - 0 .55 43 0 .019 4.8
bitvector/s3_clnt_3_true-unreach-call_true-no-overflow.BV.c.cil.c 0 900   6000 13000 - - - - 0 .74 45 0 .019 4.8
bitvector/s3_srvr_1_alt_true-unreach-call_true-no-overflow.BV.c.cil.c 0 900   6400 12000 - - - - 0 .55 41 0 .018 4.8
bitvector/s3_srvr_1_true-unreach-call_true-no-overflow.BV.c.cil.c 0 900   6500 11000 - - - - 0 .64 42 0 .019 4.9
bitvector/s3_srvr_2_alt_true-unreach-call_true-no-overflow_false-termination.BV.c.cil.c 0 910   6500 11000 - - - - 0 .42 43 0 .020 4.9
bitvector/s3_srvr_2_true-unreach-call_true-no-overflow_false-termination.BV.c.cil.c 0 900   6400 10000 - - - - 0 .67 41 0 .018 4.9
bitvector/s3_srvr_3_alt_true-unreach-call_true-no-overflow.BV.c.cil.c 0 900   6400 11000 - - - - 0 .55 43 0 .021 4.8
bitvector/s3_srvr_3_true-unreach-call_true-no-overflow.BV.c.cil.c 0 900   6500 11000 - - - - 0 .61 43 0 .019 4.9
bitvector/soft_float_1_true-unreach-call_true-no-overflow_true-termination.c.cil.c 0 900   1700 11000 - - - - 0 .47 44 0 .018 4.8
bitvector/soft_float_2_true-unreach-call_true-no-overflow_true-termination.c.cil.c 0 900   1500 10000 - - - - 0 .66 41 0 .020 5.0
bitvector/soft_float_3_true-unreach-call_true-no-overflow_true-termination.c.cil.c 0 900   1400 11000 - - - - 0 .68 43 0 .025 4.8
bitvector/soft_float_4_true-unreach-call_true-no-overflow_true-termination.c.cil.c 0 900   1500 12000 - - - - 0 .56 44 0 .019 4.9
bitvector/soft_float_5_true-unreach-call_true-no-overflow_true-termination.c.cil.c 0 900   1600 12000 - - - - 0 .68 41 0 .018 4.9
bitvector-regression/implicitfloatconversion_false-unreach-call_true-termination.c 1 8.1 240 70 1 3.1  260 1 12     230   0 3.1  190 1 .59   18    - -
bitvector-regression/implicitunsignedconversion_false-unreach-call_true-termination.c 1 4.2 240 39 1 3.0  260 1 4.9   220   0 3.5  180 1 .59   19    - -
bitvector-regression/integerpromotion_false-unreach-call_true-termination.c 1 8.2 240 74 1 2.9  260 1 6.8   220   0 2.7  180 1 .78   18    - -
bitvector-regression/recHanoi03_false-unreach-call_true-termination.c 1 120   1000 1500 1 5.4  280 -32 5.4   270   0 4.0  210 -32 .71   19    - -
bitvector-regression/signextension2_false-unreach-call_true-termination.c 1 4.1 250 40 1 3.0  250 1 4.4   220   0 3.7  180 1 .75   18    - -
bitvector-regression/signextension_false-unreach-call_true-termination.c 1 4.2 250 36 1 3.1  250 1 4.4   220   0 2.1  180 1 .65   18    - -
bitvector-regression/implicitunsignedconversion_true-unreach-call_true-termination.c 2 4.2 250 38 - - - - 2 3.0  250 2 5.0   250  
bitvector-regression/integerpromotion_true-unreach-call_true-termination.c 2 8.3 250 64 - - - - 2 3.6  250 2 9.0   230  
bitvector-regression/signextension2_true-unreach-call_true-termination.c 2 4.5 260 36 - - - - 2 4.2  250 2 6.0   260  
bitvector-regression/signextension_true-unreach-call_true-termination.c 2 4.4 260 34 - - - - 2 3.4  240 2 5.4   250  
bitvector-loops/diamond_false-unreach-call2.i 1 5.9 300 52 1 3.3  260 1 6.7   270   0 4.2  210 -32 .63   18    - -
bitvector-loops/overflow_false-unreach-call1.i 0 900   2000 11000 0 .54 41 0 .019 4.8 0 1.1  50 0 .0018 .29 - -
bitvector-loops/verisec_sendmail__tTflag_arr_one_loop_false-unreach-call_true-termination.i 0 900   4600 13000 0 .53 41 0 .018 4.9 0 1.1  49 0 .0013 .30 - -
sv-benchmarks/c/ status score witness inspect witness cpu (s) mem (MB) energy (J) status score witness inspect witness cpu (s) mem (MB) energy status score witness inspect witness cpu (s) mem (MB) energy status score witness inspect witness cpu (s) mem (MB) energy status score witness inspect witness cpu (s) mem (MB) energy status score witness inspect witness cpu (s) mem (MB) energy status score witness inspect witness cpu (s) mem (MB) energy
total 50 33 28000 110000 340000 14 -24 37   2600 14 -24 97   2700 14 0 38 2000 14 -123 6.1 170 36 24 88 4400 36 20 2200 6000
    correct results 21 33 1600 12000 19000 8 8 28   2100 8 8 92   2400 0 5 5 3.4 92 12 24 74 3300 10 20 290 3700
        correct true 12 24 1300 8300 15000 0 0 0 0 12 24 74 3300 10 20 290 3700
        correct false 9 9 270 4100 3200 8 8 28   2100 8 8 92   2400 0 5 5 3.4 92 0 0
    incorrect results 0 1 -32 6.8 280 1 -32 5.4 270 0 4 -128 2.7 76 0 0
        incorrect true 0 1 -32 6.8 280 1 -32 5.4 270 0 4 -128 2.7 76 0 0
        incorrect false 0 0 0 0 0 0 0
score (50 tasks, max score: 86) 33 -24 -24 0 -123 24 20
Run set ukojak.sv-comp18.ReachSafety-BitVectors cpa-seq-validate-violation-witnesses-ukojak.sv-comp18-violation-witness.ReachSafety-BitVectors uautomizer-validate-violation-witnesses-ukojak.sv-comp18-violation-witness.ReachSafety-BitVectors cpa-witness2test-validate-violation-witnesses-ukojak.sv-comp18-violation-witness.ReachSafety-BitVectors fshell-witness2test-validate-violation-witnesses-ukojak.sv-comp18-violation-witness.ReachSafety-BitVectors cpa-seq-validate-correctness-witnesses-ukojak.sv-comp18-correctness-witness.ReachSafety-BitVectors uautomizer-validate-correctness-witnesses-ukojak.sv-comp18-correctness-witness.ReachSafety-BitVectors