Tool ULTIMATE Automizer 0.1.23-3204b741 CPAchecker 1.6.1-svn 26773 ULTIMATE Automizer 0.1.23-3204b741 CPA-witness2test 1.6.1-svn 26773 CProver witness2test 0.1 CPAchecker 1.6.1-svn 26773 ULTIMATE Automizer 0.1.23-3204b741
Limits timelimit: 900 s, memlimit: 15000 MB, CPU core limit: 8 timelimit: 90 s, memlimit: 7000 MB, CPU core limit: 2 timelimit: 900 s, memlimit: 7000 MB, CPU core limit: 2
Host apollon*
OS Linux 4.4.0-101-generic
System CPU: Intel Xeon E3-1230 v5 @ 3.40 GHz, cores: 8, frequency: 3.8 GHz, Turbo Boost: disabled; RAM: 33553 MB CPU: Intel Xeon E3-1230 v5 @ 3.40 GHz, cores: [8; 4], frequency: 3.8 GHz, Turbo Boost: disabled; RAM: [33553 MB; 33554 MB]
Date of execution 2017-12-02 01:06:24 CET 2017-12-03 03:07:09 CET 2017-12-03 03:49:57 CET 2017-12-03 03:57:59 CET 2017-12-03 04:29:07 CET 2017-12-02 23:12:02 CET 2017-12-03 03:11:19 CET
Run set uautomizer.sv-comp18.ReachSafety-BitVectors cpa-seq-validate-violation-witnesses-uautomizer.sv-comp18-violation-witness.ReachSafety-BitVectors uautomizer-validate-violation-witnesses-uautomizer.sv-comp18-violation-witness.ReachSafety-BitVectors cpa-witness2test-validate-violation-witnesses-uautomizer.sv-comp18-violation-witness.ReachSafety-BitVectors fshell-witness2test-validate-violation-witnesses-uautomizer.sv-comp18-violation-witness.ReachSafety-BitVectors cpa-seq-validate-correctness-witnesses-uautomizer.sv-comp18-correctness-witness.ReachSafety-BitVectors uautomizer-validate-correctness-witnesses-uautomizer.sv-comp18-correctness-witness.ReachSafety-BitVectors
Options --full-output -witnessValidation -setprop witness.checkProgramHash=false -heap 5000m -benchmark -witness ../../results-verified/uautomizer.2017-12-02_0106.logfiles/sv-comp18.${inputfile_name}.files/witness.graphml -setprop cpa.predicate.memoryAllocationsAlwaysSucceed=true -setprop cpa.smg.memoryAllocationFunctions=malloc,__kmalloc,kmalloc,kzalloc,kzalloc_node,ldv_zalloc,ldv_malloc -setprop cpa.smg.arrayAllocationFunctions=calloc,kmalloc_array,kcalloc -setprop cpa.smg.zeroingMemoryAllocation=calloc,kzalloc,kcalloc,kzalloc_node,ldv_zalloc -setprop cpa.smg.deallocationFunctions=free,kfree,kfree_const --full-output --validate ../../results-verified/uautomizer.2017-12-02_0106.logfiles/sv-comp18.${inputfile_name}.files/witness.graphml -witness2test -setprop witness.checkProgramHash=false -heap 5000m -benchmark -witness ../../results-verified/uautomizer.2017-12-02_0106.logfiles/sv-comp18.${inputfile_name}.files/witness.graphml -setprop analysis.summaryEdges=true -setprop cpa.callstack.skipVoidRecursion=true -setprop cpa.callstack.skipFunctionPointerRecursion=true --graphml-witness ../../results-verified/uautomizer.2017-12-02_0106.logfiles/sv-comp18.${inputfile_name}.files/witness.graphml -witnessValidation -setprop witness.checkProgramHash=false -heap 5000m -benchmark -witness ../../results-verified/uautomizer.2017-12-02_0106.logfiles/sv-comp18.${inputfile_name}.files/witness.graphml -setprop cpa.predicate.memoryAllocationsAlwaysSucceed=true --full-output --validate ../../results-verified/uautomizer.2017-12-02_0106.logfiles/sv-comp18.${inputfile_name}.files/witness.graphml
sv-benchmarks/c/ status score witness inspect witness cpu (s) mem (MB) energy (J) status score witness inspect witness cpu (s) mem (MB) energy status score witness inspect witness cpu (s) mem (MB) energy status score witness inspect witness cpu (s) mem (MB) energy status score witness inspect witness cpu (s) mem (MB) energy status score witness inspect witness cpu (s) mem (MB) energy status score witness inspect witness cpu (s) mem (MB) energy
bitvector/byte_add_false-unreach-call_true-no-overflow_true-termination.i 1 85   880 880 1 6.1  270 1 28     520   0 5.0  210 -32 .82   19    - -
bitvector/sum02_false-unreach-call_true-no-overflow.i 0 14   380 140 0 .60 43 0 .019 5.0 0 .97 49 0 .0016 .26 - -
bitvector/byte_add_1_true-unreach-call_true-no-overflow_true-termination.i 0 900   1400 12000 - - - - 0 .68 43 0 .021 4.9
bitvector/byte_add_2_true-unreach-call_true-no-overflow_true-termination.i 0 900   1400 10000 - - - - 0 .65 42 0 .020 4.9
bitvector/gcd_1_true-unreach-call_true-no-overflow.i 0 900   630 13000 - - - - 0 .65 44 0 .020 4.8
bitvector/gcd_2_true-unreach-call_true-no-overflow.i 0 900   670 12000 - - - - 0 .70 43 0 .020 4.9
bitvector/gcd_3_true-unreach-call_true-no-overflow.i 0 900   2800 11000 - - - - 0 .61 43 0 .020 4.9
bitvector/gcd_4_true-unreach-call_true-no-overflow_true-termination.i 2 56   520 590 - - - - 2 6.3  310 2 43     560  
bitvector/interleave_bits_true-unreach-call_true-no-overflow.i 2 170   3800 2500 - - - - 2 7.4  320 2 160     630  
bitvector/jain_1_true-unreach-call_true-no-overflow_false-termination.i 2 4.7 290 40 - - - - 2 4.2  290 2 7.0   250  
bitvector/jain_2_true-unreach-call_true-no-overflow_false-termination.i 2 4.9 290 40 - - - - 2 4.8  280 2 26     330  
bitvector/jain_4_true-unreach-call_true-no-overflow_false-termination.i 2 4.9 290 38 - - - - 2 4.5  280 2 6.1   260  
bitvector/jain_5_true-unreach-call_true-no-overflow.i 0 900   700 11000 - - - - 0 .52 42 0 .019 4.9
bitvector/jain_6_true-unreach-call_true-no-overflow_false-termination.i 2 20   310 230 - - - - 2 4.9  280 2 7.5   260  
bitvector/jain_7_true-unreach-call_true-no-overflow_false-termination.i 2 4.9 290 38 - - - - 0 900    550 2 41     300  
bitvector/modulus_true-unreach-call_true-no-overflow.i 2 14   410 140 - - - - 2 15    330 2 14     320  
bitvector/num_conversion_1_true-unreach-call_true-no-overflow.i 2 270   3300 3300 - - - - 2 4.9  290 2 51     610  
bitvector/num_conversion_2_true-unreach-call_true-no-overflow.i 0 900   1300 8800 - - - - 0 .58 42 0 .028 4.8
bitvector/parity_true-unreach-call_true-no-overflow.i 0 900   1000 12000 - - - - 0 .70 41 0 .022 4.9
bitvector/sum02_true-unreach-call_true-no-overflow.i 0 900   560 11000 - - - - 0 .67 41 0 .020 4.8
bitvector/s3_clnt_1_false-unreach-call_true-no-overflow.BV.c.cil.c 1 24   710 180 -32 6.3  270 1 17     450   0 5.2  230 -32 .66   20    - -
bitvector/s3_clnt_2_false-unreach-call_true-no-overflow.BV.c.cil.c 1 27   650 210 -32 6.0  280 1 21     490   0 4.4  220 -32 .86   20    - -
bitvector/s3_clnt_3_false-unreach-call_true-no-overflow.BV.c.cil.c 1 23   580 170 -32 7.9  280 1 20     390   0 5.2  240 -32 .76   20    - -
bitvector/s3_clnt_1_true-unreach-call_true-no-overflow.BV.c.cil.c 2 41   1300 380 - - - - 2 77    830 2 40     760  
bitvector/s3_clnt_2_true-unreach-call_true-no-overflow.BV.c.cil.c 2 43   1900 360 - - - - 2 17    450 2 46     940  
bitvector/s3_clnt_3_true-unreach-call_true-no-overflow.BV.c.cil.c 2 25   1000 190 - - - - 2 15    410 0 120     7000  
bitvector/s3_srvr_1_alt_true-unreach-call_true-no-overflow.BV.c.cil.c 0 900   2100 13000 - - - - 0 .61 43 0 .021 5.0
bitvector/s3_srvr_1_true-unreach-call_true-no-overflow.BV.c.cil.c 2 53   2200 490 - - - - 0 910    4800 2 47     1100  
bitvector/s3_srvr_2_alt_true-unreach-call_true-no-overflow_false-termination.BV.c.cil.c 2 40   1800 350 - - - - 0 900    4000 2 33     1100  
bitvector/s3_srvr_2_true-unreach-call_true-no-overflow_false-termination.BV.c.cil.c 2 41   1800 350 - - - - 0 900    3900 2 32     1100  
bitvector/s3_srvr_3_alt_true-unreach-call_true-no-overflow.BV.c.cil.c 2 40   1500 390 - - - - 0 910    5300 2 36     990  
bitvector/s3_srvr_3_true-unreach-call_true-no-overflow.BV.c.cil.c 2 39   1500 330 - - - - 0 910    5400 2 29     950  
bitvector/soft_float_1_true-unreach-call_true-no-overflow_true-termination.c.cil.c 0 110   850 1200 - - - - 0 .63 41 0 .021 4.8
bitvector/soft_float_2_true-unreach-call_true-no-overflow_true-termination.c.cil.c 2 26   750 210 - - - - 0 900    6300 2 62     700  
bitvector/soft_float_3_true-unreach-call_true-no-overflow_true-termination.c.cil.c 0 900   890 9600 - - - - 0 .53 43 0 .022 4.9
bitvector/soft_float_4_true-unreach-call_true-no-overflow_true-termination.c.cil.c 0 490   910 6400 - - - - 0 .66 41 0 .019 5.0
bitvector/soft_float_5_true-unreach-call_true-no-overflow_true-termination.c.cil.c 2 22   680 210 - - - - 0 900    6300 2 24     610  
bitvector-regression/implicitfloatconversion_false-unreach-call_true-termination.c 1 8.0 240 58 1 4.0  270 1 9.5   220   0 2.6  180 1 .63   18    - -
bitvector-regression/implicitunsignedconversion_false-unreach-call_true-termination.c 1 4.0 240 39 1 3.5  260 1 3.1   220   0 2.9  180 1 .80   18    - -
bitvector-regression/integerpromotion_false-unreach-call_true-termination.c 1 8.0 240 64 1 3.2  250 1 9.1   220   0 3.7  190 1 .59   18    - -
bitvector-regression/recHanoi03_false-unreach-call_true-termination.c 1 210   1300 2900 1 5.2  280 -32 6.3   260   0 4.2  220 -32 .74   19    - -
bitvector-regression/signextension2_false-unreach-call_true-termination.c 1 4.0 230 36 1 3.4  260 1 4.3   220   0 3.4  190 1 .69   18    - -
bitvector-regression/signextension_false-unreach-call_true-termination.c 1 4.1 240 36 1 3.7  250 1 5.3   220   0 2.7  190 1 .70   18    - -
bitvector-regression/implicitunsignedconversion_true-unreach-call_true-termination.c 2 4.5 270 38 - - - - 2 3.0  250 2 4.8   250  
bitvector-regression/integerpromotion_true-unreach-call_true-termination.c 2 8.7 280 67 - - - - 2 3.3  250 2 10     270  
bitvector-regression/signextension2_true-unreach-call_true-termination.c 2 4.5 280 35 - - - - 2 3.1  250 2 6.6   260  
bitvector-regression/signextension_true-unreach-call_true-termination.c 2 4.8 290 37 - - - - 2 3.1  250 2 6.5   260  
bitvector-loops/diamond_false-unreach-call2.i 1 7.2 340 63 1 3.7  260 1 5.8   260   0 3.2  210 -32 .61   19    - -
bitvector-loops/overflow_false-unreach-call1.i 0 900   710 12000 0 .57 43 0 .022 5.0 0 .99 50 0 .0015 .28 - -
bitvector-loops/verisec_sendmail__tTflag_arr_one_loop_false-unreach-call_true-termination.i 1 470   780 5400 1 4.4  280 0 40     7000   0 3.2  210 -32 .58   19    - -
sv-benchmarks/c/ status score witness inspect witness cpu (s) mem (MB) energy (J) status score witness inspect witness cpu (s) mem (MB) energy status score witness inspect witness cpu (s) mem (MB) energy status score witness inspect witness cpu (s) mem (MB) energy status score witness inspect witness cpu (s) mem (MB) energy status score witness inspect witness cpu (s) mem (MB) energy status score witness inspect witness cpu (s) mem (MB) energy
total 50 58 13000 48000 160000 14 -87 59 3300 14 -22 170   10000 14 0 48 2600 14 -219 8.4 230 36 30 7400 42000 36 44 850 20000
    correct results 35 58 1800 31000 20000 9 9 37 2400 10 10 120   3200 0 5 5 3.4 92 15 30 170 5100 22 44 730 13000
        correct true 23 46 940 25000 10000 0 0 0 0 15 30 170 5100 22 44 730 13000
        correct false 12 12 880 6500 10000 9 9 37 2400 10 10 120   3200 0 5 5 3.4 92 0 0
    incorrect results 0 3 -96 20 830 1 -32 6.3 260 0 7 -224 5.0 140 0 0
        incorrect true 0 3 -96 20 830 1 -32 6.3 260 0 7 -224 5.0 140 0 0
        incorrect false 0 0 0 0 0 0 0
score (50 tasks, max score: 86) 58 -87 -22 0 -219 30 44
Run set uautomizer.sv-comp18.ReachSafety-BitVectors cpa-seq-validate-violation-witnesses-uautomizer.sv-comp18-violation-witness.ReachSafety-BitVectors uautomizer-validate-violation-witnesses-uautomizer.sv-comp18-violation-witness.ReachSafety-BitVectors cpa-witness2test-validate-violation-witnesses-uautomizer.sv-comp18-violation-witness.ReachSafety-BitVectors fshell-witness2test-validate-violation-witnesses-uautomizer.sv-comp18-violation-witness.ReachSafety-BitVectors cpa-seq-validate-correctness-witnesses-uautomizer.sv-comp18-correctness-witness.ReachSafety-BitVectors uautomizer-validate-correctness-witnesses-uautomizer.sv-comp18-correctness-witness.ReachSafety-BitVectors