Tool ESBMC ESBMC version 4.6.0 64-bit x86_64 linux CPAchecker 1.6.1-svn 26773 ULTIMATE Automizer 0.1.23-3204b741 CPA-witness2test 1.6.1-svn 26773 CProver witness2test 0.1 CPAchecker 1.6.1-svn 26773 ULTIMATE Automizer 0.1.23-3204b741
Limits timelimit: 900 s, memlimit: 15000 MB, CPU core limit: 8 timelimit: 90 s, memlimit: 7000 MB, CPU core limit: 2 timelimit: 900 s, memlimit: 7000 MB, CPU core limit: 2
Host apollon* [apollon010; apollon035; apollon045; apollon077; apollon078; apollon138] [apollon007; apollon077; apollon078; apollon143] apollon*
OS Linux 4.4.0-101-generic
System CPU: Intel Xeon E3-1230 v5 @ 3.40 GHz, cores: 8, frequency: 3.8 GHz, Turbo Boost: disabled; RAM: 33553 MB CPU: Intel Xeon E3-1230 v5 @ 3.40 GHz, cores: [8; 4], frequency: 3.8 GHz, Turbo Boost: disabled; RAM: [33553 MB; 33554 MB]
Date of execution 2017-12-01 08:49:27 CET 2017-12-01 22:53:44 CET 2017-12-01 23:38:04 CET 2017-12-01 23:47:42 CET 2017-12-01 23:55:24 CET 2017-12-01 22:20:30 CET 2017-12-01 23:01:53 CET
Run set esbmc-incr.sv-comp18.ReachSafety-BitVectors cpa-seq-validate-violation-witnesses-esbmc-incr.sv-comp18-violation-witness.ReachSafety-BitVectors uautomizer-validate-violation-witnesses-esbmc-incr.sv-comp18-violation-witness.ReachSafety-BitVectors cpa-witness2test-validate-violation-witnesses-esbmc-incr.sv-comp18-violation-witness.ReachSafety-BitVectors fshell-witness2test-validate-violation-witnesses-esbmc-incr.sv-comp18-violation-witness.ReachSafety-BitVectors cpa-seq-validate-correctness-witnesses-esbmc-incr.sv-comp18-correctness-witness.ReachSafety-BitVectors uautomizer-validate-correctness-witnesses-esbmc-incr.sv-comp18-correctness-witness.ReachSafety-BitVectors
Options -s incr -witnessValidation -setprop witness.checkProgramHash=false -heap 5000m -benchmark -witness ../../results-verified/esbmc-incr.2017-12-01_0849.logfiles/sv-comp18.${inputfile_name}.files/witness.graphml -setprop cpa.predicate.memoryAllocationsAlwaysSucceed=true -setprop cpa.smg.memoryAllocationFunctions=malloc,__kmalloc,kmalloc,kzalloc,kzalloc_node,ldv_zalloc,ldv_malloc -setprop cpa.smg.arrayAllocationFunctions=calloc,kmalloc_array,kcalloc -setprop cpa.smg.zeroingMemoryAllocation=calloc,kzalloc,kcalloc,kzalloc_node,ldv_zalloc -setprop cpa.smg.deallocationFunctions=free,kfree,kfree_const --full-output --validate ../../results-verified/esbmc-incr.2017-12-01_0849.logfiles/sv-comp18.${inputfile_name}.files/witness.graphml -witness2test -setprop witness.checkProgramHash=false -heap 5000m -benchmark -witness ../../results-verified/esbmc-incr.2017-12-01_0849.logfiles/sv-comp18.${inputfile_name}.files/witness.graphml -setprop analysis.summaryEdges=true -setprop cpa.callstack.skipVoidRecursion=true -setprop cpa.callstack.skipFunctionPointerRecursion=true --graphml-witness ../../results-verified/esbmc-incr.2017-12-01_0849.logfiles/sv-comp18.${inputfile_name}.files/witness.graphml -witnessValidation -setprop witness.checkProgramHash=false -heap 5000m -benchmark -witness ../../results-verified/esbmc-incr.2017-12-01_0849.logfiles/sv-comp18.${inputfile_name}.files/witness.graphml -setprop cpa.predicate.memoryAllocationsAlwaysSucceed=true --full-output --validate ../../results-verified/esbmc-incr.2017-12-01_0849.logfiles/sv-comp18.${inputfile_name}.files/witness.graphml
sv-benchmarks/c/ status score witness inspect witness cpu (s) mem (MB) energy (J) status score witness inspect witness cpu (s) mem (MB) energy status score witness inspect witness cpu (s) mem (MB) energy status score witness inspect witness cpu (s) mem (MB) energy status score witness inspect witness cpu (s) mem (MB) energy status score witness inspect witness cpu (s) mem (MB) energy status score witness inspect witness cpu (s) mem (MB) energy
bitvector/byte_add_false-unreach-call_true-no-overflow_true-termination.i 1 1.1   29 10    1 4.7  270 -32 4.5   280   0 3.2  220 1 .59   18    - -
bitvector/sum02_false-unreach-call_true-no-overflow.i 0 900     780 11000    0 .57 42 0 .021 5.0 0 .85 49 0 .0011 .28 - -
bitvector/byte_add_1_true-unreach-call_true-no-overflow_true-termination.i 2 .18  27 1.6  - - - - 2 9.0  340 0 960     1100  
bitvector/byte_add_2_true-unreach-call_true-no-overflow_true-termination.i 2 .17  27 2.0  - - - - 2 9.8  330 0 960     1100  
bitvector/gcd_1_true-unreach-call_true-no-overflow.i 2 .97  29 12    - - - - 2 12    300 0 960     1700  
bitvector/gcd_2_true-unreach-call_true-no-overflow.i 2 27     45 330    - - - - 2 120    460 0 960     610  
bitvector/gcd_3_true-unreach-call_true-no-overflow.i 2 30     43 370    - - - - 2 160    460 0 310     950  
bitvector/gcd_4_true-unreach-call_true-no-overflow_true-termination.i 2 .082 27 .78 - - - - 2 5.7  310 2 52     560  
bitvector/interleave_bits_true-unreach-call_true-no-overflow.i 2 .099 26 1.1  - - - - 2 5.7  300 2 190     630  
bitvector/jain_1_true-unreach-call_true-no-overflow_false-termination.i 0 900     1200 9800    - - - - 0 .63 43 0 .018 4.8
bitvector/jain_2_true-unreach-call_true-no-overflow_false-termination.i 0 900     830 10000    - - - - 0 .70 43 0 .018 4.9
bitvector/jain_4_true-unreach-call_true-no-overflow_false-termination.i 0 900     750 9700    - - - - 0 .62 43 0 .022 4.9
bitvector/jain_5_true-unreach-call_true-no-overflow.i 0 900     11000 10000    - - - - 0 .66 41 0 .018 4.8
bitvector/jain_6_true-unreach-call_true-no-overflow_false-termination.i 0 900     750 9100    - - - - 0 .70 45 0 .022 4.9
bitvector/jain_7_true-unreach-call_true-no-overflow_false-termination.i 0 900     1000 9700    - - - - 0 .53 43 0 .019 4.9
bitvector/modulus_true-unreach-call_true-no-overflow.i 2 180     280 2100    - - - - 2 15    310 2 12     330  
bitvector/num_conversion_1_true-unreach-call_true-no-overflow.i 2 .090 26 .92 - - - - 2 4.2  260 2 73     650  
bitvector/num_conversion_2_true-unreach-call_true-no-overflow.i 2 .12  26 .88 - - - - 2 5.2  270 0 960     1100  
bitvector/parity_true-unreach-call_true-no-overflow.i 2 7.0   28 93    - - - - 2 25    320 0 960     1000  
bitvector/sum02_true-unreach-call_true-no-overflow.i 0 900     760 12000    - - - - 0 .59 44 0 .023 4.9
bitvector/s3_clnt_1_false-unreach-call_true-no-overflow.BV.c.cil.c 1 5.9   87 60    1 4.9  280 -32 4.4   260   0 3.1  220 -32 .64   19    - -
bitvector/s3_clnt_2_false-unreach-call_true-no-overflow.BV.c.cil.c 1 6.1   96 63    1 6.5  280 -32 4.2   260   0 3.0  220 -32 .63   19    - -
bitvector/s3_clnt_3_false-unreach-call_true-no-overflow.BV.c.cil.c 1 2.6   58 26    1 4.6  270 -32 4.2   260   0 4.2  220 -32 .63   19    - -
bitvector/s3_clnt_1_true-unreach-call_true-no-overflow.BV.c.cil.c 2 22     190 260    - - - - 2 73    760 2 41     770  
bitvector/s3_clnt_2_true-unreach-call_true-no-overflow.BV.c.cil.c 2 11     160 130    - - - - 2 19    450 2 44     1100  
bitvector/s3_clnt_3_true-unreach-call_true-no-overflow.BV.c.cil.c 2 10     150 110    - - - - 2 13    510 2 34     790  
bitvector/s3_srvr_1_alt_true-unreach-call_true-no-overflow.BV.c.cil.c 0 900     360 11000    - - - - 0 .58 44 0 .019 4.8
bitvector/s3_srvr_1_true-unreach-call_true-no-overflow.BV.c.cil.c 0 900     2300 8400    - - - - 0 .54 45 0 .018 4.9
bitvector/s3_srvr_2_alt_true-unreach-call_true-no-overflow_false-termination.BV.c.cil.c 0 900     2100 12000    - - - - 0 .71 43 0 .018 4.8
bitvector/s3_srvr_2_true-unreach-call_true-no-overflow_false-termination.BV.c.cil.c 0 900     2100 8300    - - - - 0 .67 42 0 .018 5.0
bitvector/s3_srvr_3_alt_true-unreach-call_true-no-overflow.BV.c.cil.c 0 900     1800 9500    - - - - 0 .66 44 0 .018 4.8
bitvector/s3_srvr_3_true-unreach-call_true-no-overflow.BV.c.cil.c 0 900     1800 12000    - - - - 0 .61 43 0 .020 5.0
bitvector/soft_float_1_true-unreach-call_true-no-overflow_true-termination.c.cil.c 2 4.3   34 52    - - - - 0 920    6400 2 120     770  
bitvector/soft_float_2_true-unreach-call_true-no-overflow_true-termination.c.cil.c 2 .65  32 7.4  - - - - 0 910    6300 2 62     700  
bitvector/soft_float_3_true-unreach-call_true-no-overflow_true-termination.c.cil.c 1 .47  30 5.5  - - - - 0 900    6100 0 960     770  
bitvector/soft_float_4_true-unreach-call_true-no-overflow_true-termination.c.cil.c 2 23     35 310    - - - - 2 250    580 2 320     850  
bitvector/soft_float_5_true-unreach-call_true-no-overflow_true-termination.c.cil.c 2 .67  32 8.5  - - - - 0 900    6300 2 22     610  
bitvector-regression/implicitfloatconversion_false-unreach-call_true-termination.c 1 .11  28 .83 1 3.3  270 1 8.9   240   0 1.9  180 1 .57   18    - -
bitvector-regression/implicitunsignedconversion_false-unreach-call_true-termination.c 1 .11  28 .85 1 3.5  260 1 4.4   220   0 2.0  180 1 .57   18    - -
bitvector-regression/integerpromotion_false-unreach-call_true-termination.c 1 .13  28 1.1  1 3.1  250 1 8.9   220   0 2.7  210 1 .57   18    - -
bitvector-regression/recHanoi03_false-unreach-call_true-termination.c 1 .75  28 8.6  0 91    1600 -32 11     260   0 2.8  180 1 .58   18    - -
bitvector-regression/signextension2_false-unreach-call_true-termination.c 1 .091 28 .91 1 3.6  260 1 4.6   220   0 2.7  210 1 .56   18    - -
bitvector-regression/signextension_false-unreach-call_true-termination.c 1 .080 28 .96 1 4.3  260 1 4.5   220   0 2.7  180 1 .57   18    - -
bitvector-regression/implicitunsignedconversion_true-unreach-call_true-termination.c 2 .070 26 .89 - - - - 2 3.4  250 2 4.9   250  
bitvector-regression/integerpromotion_true-unreach-call_true-termination.c 2 .089 26 .69 - - - - 2 3.6  240 2 9.2   220  
bitvector-regression/signextension2_true-unreach-call_true-termination.c 2 .072 26 .81 - - - - 2 3.0  240 2 4.9   260  
bitvector-regression/signextension_true-unreach-call_true-termination.c 2 .097 26 .74 - - - - 2 3.5  250 2 6.0   260  
bitvector-loops/diamond_false-unreach-call2.i 1 .55  28 4.8  1 3.7  260 1 6.1   260   0 3.2  210 1 .60   18    - -
bitvector-loops/overflow_false-unreach-call1.i 0 900     11000 11000    0 .60 44 0 .018 4.8 0 .83 49 0 .0012 .27 - -
bitvector-loops/verisec_sendmail__tTflag_arr_one_loop_false-unreach-call_true-termination.i 0 2.1   30 18    -32 3.7  260 0 98     5900   0 2.3  210 -32 .58   18    - -
sv-benchmarks/c/ status score witness inspect witness cpu (s) mem (MB) energy (J) status score witness inspect witness cpu (s) mem (MB) energy status score witness inspect witness cpu (s) mem (MB) energy status score witness inspect witness cpu (s) mem (MB) energy status score witness inspect witness cpu (s) mem (MB) energy status score witness inspect witness cpu (s) mem (MB) energy status score witness inspect witness cpu (s) mem (MB) energy
total 50 56 14000    40000 160000   14 -22 140   4600 14 -154 160 8600 14 0 36 2600 14 -120 7.1 220 36 38 4400 33000 36 30 8000 17000
    correct results 33 55 330    1800 4000   10 10 42   2700 6 6 37 1400 0 8 8 4.6 150 19 38 740 7000 15 30 1000 8800
        correct true 22 44 320    1300 3800   0 0 0 0 19 38 740 7000 15 30 1000 8800
        correct false 11 11 18    460 180   10 10 42   2700 6 6 37 1400 0 8 8 4.6 150 0 0
    correct-unconfimed results 2 1 2.6  60 24   0 0 0 0 0 0
        correct-unconfirmed true 1 1 .47 30 5.5 0 0 0 0 0 0
        correct-unconfirmed false 1 0 2.1  30 18   0 0 0 0 0 0
    incorrect results 0 1 -32 3.7 260 5 -160 28 1300 0 4 -128 2.5 75 0 0
        incorrect true 0 1 -32 3.7 260 5 -160 28 1300 0 4 -128 2.5 75 0 0
        incorrect false 0 0 0 0 0 0 0
score (50 tasks, max score: 86) 56 -22 -154 0 -120 38 30
Run set esbmc-incr.sv-comp18.ReachSafety-BitVectors cpa-seq-validate-violation-witnesses-esbmc-incr.sv-comp18-violation-witness.ReachSafety-BitVectors uautomizer-validate-violation-witnesses-esbmc-incr.sv-comp18-violation-witness.ReachSafety-BitVectors cpa-witness2test-validate-violation-witnesses-esbmc-incr.sv-comp18-violation-witness.ReachSafety-BitVectors fshell-witness2test-validate-violation-witnesses-esbmc-incr.sv-comp18-violation-witness.ReachSafety-BitVectors cpa-seq-validate-correctness-witnesses-esbmc-incr.sv-comp18-correctness-witness.ReachSafety-BitVectors uautomizer-validate-correctness-witnesses-esbmc-incr.sv-comp18-correctness-witness.ReachSafety-BitVectors