Tool CPAchecker 1.6.1-svn 26725 CPAchecker 1.6.1-svn 26773 ULTIMATE Automizer 0.1.23-3204b741 CPA-witness2test 1.6.1-svn 26773 CProver witness2test 0.1 CPAchecker 1.6.1-svn 26773 ULTIMATE Automizer 0.1.23-3204b741
Limits timelimit: 900 s, memlimit: 15000 MB, CPU core limit: 8 timelimit: 90 s, memlimit: 7000 MB, CPU core limit: 2 timelimit: 900 s, memlimit: 7000 MB, CPU core limit: 2
Host apollon*
OS Linux 4.4.0-101-generic
System CPU: Intel Xeon E3-1230 v5 @ 3.40 GHz, cores: 8, frequency: 3.8 GHz, Turbo Boost: disabled; RAM: 33553 MB CPU: Intel Xeon E3-1230 v5 @ 3.40 GHz, cores: [8; 4], frequency: 3.8 GHz, Turbo Boost: disabled; RAM: [33553 MB; 33554 MB]
Date of execution 2017-11-30 11:20:26 CET 2017-12-01 07:36:53 CET 2017-12-01 08:24:12 CET 2017-12-01 08:27:09 CET 2017-12-01 08:31:26 CET 2017-12-01 04:24:37 CET 2017-12-01 07:42:15 CET
Run set cpa-bam-bnb.sv-comp18.ReachSafety-BitVectors cpa-seq-validate-violation-witnesses-cpa-bam-bnb.sv-comp18-violation-witness.ReachSafety-BitVectors uautomizer-validate-violation-witnesses-cpa-bam-bnb.sv-comp18-violation-witness.ReachSafety-BitVectors cpa-witness2test-validate-violation-witnesses-cpa-bam-bnb.sv-comp18-violation-witness.ReachSafety-BitVectors fshell-witness2test-validate-violation-witnesses-cpa-bam-bnb.sv-comp18-violation-witness.ReachSafety-BitVectors cpa-seq-validate-correctness-witnesses-cpa-bam-bnb.sv-comp18-correctness-witness.ReachSafety-BitVectors uautomizer-validate-correctness-witnesses-cpa-bam-bnb.sv-comp18-correctness-witness.ReachSafety-BitVectors
Options -svcomp18-bam-bnb -disable-java-assertions -heap 10000m -witnessValidation -setprop witness.checkProgramHash=false -heap 5000m -benchmark -witness ../../results-verified/cpa-bam-bnb.2017-11-30_1120.logfiles/sv-comp18.${inputfile_name}.files/witness.graphml -setprop cpa.predicate.memoryAllocationsAlwaysSucceed=true -setprop cpa.smg.memoryAllocationFunctions=malloc,__kmalloc,kmalloc,kzalloc,kzalloc_node,ldv_zalloc,ldv_malloc -setprop cpa.smg.arrayAllocationFunctions=calloc,kmalloc_array,kcalloc -setprop cpa.smg.zeroingMemoryAllocation=calloc,kzalloc,kcalloc,kzalloc_node,ldv_zalloc -setprop cpa.smg.deallocationFunctions=free,kfree,kfree_const --full-output --validate ../../results-verified/cpa-bam-bnb.2017-11-30_1120.logfiles/sv-comp18.${inputfile_name}.files/witness.graphml -witness2test -setprop witness.checkProgramHash=false -heap 5000m -benchmark -witness ../../results-verified/cpa-bam-bnb.2017-11-30_1120.logfiles/sv-comp18.${inputfile_name}.files/witness.graphml -setprop analysis.summaryEdges=true -setprop cpa.callstack.skipVoidRecursion=true -setprop cpa.callstack.skipFunctionPointerRecursion=true --graphml-witness ../../results-verified/cpa-bam-bnb.2017-11-30_1120.logfiles/sv-comp18.${inputfile_name}.files/witness.graphml -witnessValidation -setprop witness.checkProgramHash=false -heap 5000m -benchmark -witness ../../results-verified/cpa-bam-bnb.2017-11-30_1120.logfiles/sv-comp18.${inputfile_name}.files/witness.graphml -setprop cpa.predicate.memoryAllocationsAlwaysSucceed=true --full-output --validate ../../results-verified/cpa-bam-bnb.2017-11-30_1120.logfiles/sv-comp18.${inputfile_name}.files/witness.graphml
sv-benchmarks/c/ status score witness inspect witness cpu (s) mem (MB) energy (J) status score witness inspect witness cpu (s) mem (MB) energy status score witness inspect witness cpu (s) mem (MB) energy status score witness inspect witness cpu (s) mem (MB) energy status score witness inspect witness cpu (s) mem (MB) energy status score witness inspect witness cpu (s) mem (MB) energy status score witness inspect witness cpu (s) mem (MB) energy
bitvector/byte_add_false-unreach-call_true-no-overflow_true-termination.i 0 11   470 87 0 .56 43 0 .023 4.9 0 .81 49 0 .0014 .26 - -
bitvector/sum02_false-unreach-call_true-no-overflow.i 0 3.6 290 32 0 .53 43 0 .024 4.8 0 .85 47 0 .0011 .26 - -
bitvector/byte_add_1_true-unreach-call_true-no-overflow_true-termination.i 0 9.5 480 75 - - - - 0 .66 42 0 .018 4.9
bitvector/byte_add_2_true-unreach-call_true-no-overflow_true-termination.i 0 13   520 100 - - - - 0 .56 43 0 .025 4.8
bitvector/gcd_1_true-unreach-call_true-no-overflow.i 0 7.4 310 90 - - - - 0 .65 43 0 .024 5.0
bitvector/gcd_2_true-unreach-call_true-no-overflow.i 2 3.9 280 31 - - - - 2 140    470 0 820     950  
bitvector/gcd_3_true-unreach-call_true-no-overflow.i 0 5.3 300 49 - - - - 0 .64 43 0 .019 4.9
bitvector/gcd_4_true-unreach-call_true-no-overflow_true-termination.i 2 3.3 270 32 - - - - 2 7.1  320 -16 5.6   260  
bitvector/interleave_bits_true-unreach-call_true-no-overflow.i 0 5.9 380 49 - - - - 0 .55 42 0 .025 4.8
bitvector/jain_1_true-unreach-call_true-no-overflow_false-termination.i 2 3.0 270 26 - - - - 0 910    5900 2 6.0   260  
bitvector/jain_2_true-unreach-call_true-no-overflow_false-termination.i 2 3.2 280 28 - - - - 0 770    7000 2 5.3   270  
bitvector/jain_4_true-unreach-call_true-no-overflow_false-termination.i 2 3.2 270 25 - - - - 0 710    7000 2 5.3   260  
bitvector/jain_5_true-unreach-call_true-no-overflow.i 0 900   3900 10000 - - - - 0 .71 45 0 .020 4.9
bitvector/jain_6_true-unreach-call_true-no-overflow_false-termination.i 2 3.2 280 32 - - - - 0 580    7000 2 23     340  
bitvector/jain_7_true-unreach-call_true-no-overflow_false-termination.i 2 3.2 280 30 - - - - 0 810    7000 2 5.1   260  
bitvector/modulus_true-unreach-call_true-no-overflow.i 0 18   310 240 - - - - 0 .64 44 0 .018 4.8
bitvector/num_conversion_1_true-unreach-call_true-no-overflow.i 2 3.3 280 34 - - - - 2 5.5  270 2 49     630  
bitvector/num_conversion_2_true-unreach-call_true-no-overflow.i 0 900   330 12000 - - - - 0 .56 43 0 .023 4.9
bitvector/parity_true-unreach-call_true-no-overflow.i 0 3.5 290 29 - - - - 0 .59 43 0 .019 4.9
bitvector/sum02_true-unreach-call_true-no-overflow.i 0 3.4 290 31 - - - - 0 .52 43 0 .023 4.9
bitvector/s3_clnt_1_false-unreach-call_true-no-overflow.BV.c.cil.c 0 900   4400 12000 0 .57 44 0 .023 5.0 0 1.1  49 0 .0012 .34 - -
bitvector/s3_clnt_2_false-unreach-call_true-no-overflow.BV.c.cil.c 1 27   1100 210 1 5.7  280 1 23     490   0 4.5  220 -32 .68   20    - -
bitvector/s3_clnt_3_false-unreach-call_true-no-overflow.BV.c.cil.c 0 6.9 400 66 0 .52 43 0 .020 4.8 0 .93 49 0 .0012 .26 - -
bitvector/s3_clnt_1_true-unreach-call_true-no-overflow.BV.c.cil.c 0 900   4400 10000 - - - - 0 .54 42 0 .021 4.8
bitvector/s3_clnt_2_true-unreach-call_true-no-overflow.BV.c.cil.c 2 38   2000 260 - - - - 2 17    450 2 46     970  
bitvector/s3_clnt_3_true-unreach-call_true-no-overflow.BV.c.cil.c 2 27   1100 210 - - - - 2 15    410 2 37     840  
bitvector/s3_srvr_1_alt_true-unreach-call_true-no-overflow.BV.c.cil.c 0 900   6700 9000 - - - - 0 .56 43 0 .022 4.8
bitvector/s3_srvr_1_true-unreach-call_true-no-overflow.BV.c.cil.c 2 11   510 86 - - - - 0 900    4600 2 50     1100  
bitvector/s3_srvr_2_alt_true-unreach-call_true-no-overflow_false-termination.BV.c.cil.c 2 11   500 87 - - - - 0 900    4000 2 36     1100  
bitvector/s3_srvr_2_true-unreach-call_true-no-overflow_false-termination.BV.c.cil.c 2 12   520 95 - - - - 0 900    3900 2 33     1100  
bitvector/s3_srvr_3_alt_true-unreach-call_true-no-overflow.BV.c.cil.c 0 900   4100 11000 - - - - 0 .52 41 0 .019 4.8
bitvector/s3_srvr_3_true-unreach-call_true-no-overflow.BV.c.cil.c 0 900   4100 11000 - - - - 0 .54 43 0 .019 4.9
bitvector/soft_float_1_true-unreach-call_true-no-overflow_true-termination.c.cil.c 0 5.0 320 47 - - - - 0 .64 43 0 .019 5.0
bitvector/soft_float_2_true-unreach-call_true-no-overflow_true-termination.c.cil.c 0 5.5 300 43 - - - - 0 .73 44 0 .023 4.9
bitvector/soft_float_3_true-unreach-call_true-no-overflow_true-termination.c.cil.c 0 5.2 300 41 - - - - 0 .60 43 0 .021 5.0
bitvector/soft_float_4_true-unreach-call_true-no-overflow_true-termination.c.cil.c 0 4.6 320 41 - - - - 0 .56 43 0 .020 5.0
bitvector/soft_float_5_true-unreach-call_true-no-overflow_true-termination.c.cil.c 0 5.6 320 48 - - - - 0 .64 42 0 .022 4.9
bitvector-regression/implicitfloatconversion_false-unreach-call_true-termination.c 1 3.1 280 27 1 3.4  260 1 11     220   0 2.7  180 1 .63   18    - -
bitvector-regression/implicitunsignedconversion_false-unreach-call_true-termination.c -32 2.8 270 24 1 4.4  250 1 4.5   220   0 .89 52 0 .074  9.0  - -
bitvector-regression/integerpromotion_false-unreach-call_true-termination.c 1 3.1 280 26 1 3.9  260 1 12     220   0 3.0  180 1 .59   18    - -
bitvector-regression/recHanoi03_false-unreach-call_true-termination.c 0 3.3 290 30 0 91    1800 -32 21     410   0 2.9  210 -32 .57   18    - -
bitvector-regression/signextension2_false-unreach-call_true-termination.c -32 2.8 270 25 1 3.7  250 1 4.7   220   0 1.2  51 0 .066  9.0  - -
bitvector-regression/signextension_false-unreach-call_true-termination.c -32 2.8 270 27 1 4.6  250 1 4.3   220   0 .91 51 0 .070  9.0  - -
bitvector-regression/implicitunsignedconversion_true-unreach-call_true-termination.c 2 2.8 270 25 - - - - 2 2.8  250 2 6.4   250  
bitvector-regression/integerpromotion_true-unreach-call_true-termination.c 2 3.0 270 25 - - - - 2 3.6  250 2 9.3   250  
bitvector-regression/signextension2_true-unreach-call_true-termination.c 2 2.8 270 24 - - - - 2 2.9  250 2 6.3   260  
bitvector-regression/signextension_true-unreach-call_true-termination.c 2 2.9 270 25 - - - - 2 3.0  250 2 5.7   260  
bitvector-loops/diamond_false-unreach-call2.i -32 9.8 480 78 0 6.5  280 1 10     330   0 1.1  54 0 .069  9.1  - -
bitvector-loops/overflow_false-unreach-call1.i -32 3.1 280 27 0 92    1700 1 5.7   260   0 .99 51 0 .068  9.1  - -
bitvector-loops/verisec_sendmail__tTflag_arr_one_loop_false-unreach-call_true-termination.i -32 3.4 280 31 -32 4.8  270 0 97     560   0 1.0  51 0 .072  9.0  - -
sv-benchmarks/c/ status score witness inspect witness cpu (s) mem (MB) energy (J) status score witness inspect witness cpu (s) mem (MB) energy status score witness inspect witness cpu (s) mem (MB) energy status score witness inspect witness cpu (s) mem (MB) energy status score witness inspect witness cpu (s) mem (MB) energy status score witness inspect witness cpu (s) mem (MB) energy status score witness inspect witness cpu (s) mem (MB) energy
total 50 -155 6600   45000 78000 14 -26 220   5700 14 -24 190 3200 14 0 23 1300 14 -62 2.9 130 36 18 6700 50000 36 14 1200   9400
    correct results 20 37 170   9500 1300 6 6 26   1600 8 8 75 2200 0 2 2 1.2 37 9 18 190 2900 15 30 320   8100
        correct true 17 34 140   7900 1100 0 0 0 0 9 18 190 2900 15 30 320   8100
        correct false 3 3 33   1700 260 6 6 26   1600 8 8 75 2200 0 2 2 1.2 37 0 0
    correct-unconfimed results 1 0 3.3 290 30 0 0 0 0 0 0
        correct-unconfirmed true 0 0 0 0 0 0 0
        correct-unconfirmed false 1 0 3.3 290 30 0 0 0 0 0 0
    incorrect results 6 -192 25   1900 210 1 -32 4.8 270 1 -32 21 410 0 2 -64 1.2 39 0 1 -16 5.6 260
        incorrect true 6 -192 25   1900 210 1 -32 4.8 270 1 -32 21 410 0 2 -64 1.2 39 0 0
        incorrect false 0 0 0 0 0 0 1 -16 5.6 260
score (50 tasks, max score: 86) -155 -26 -24 0 -62 18 14
Run set cpa-bam-bnb.sv-comp18.ReachSafety-BitVectors cpa-seq-validate-violation-witnesses-cpa-bam-bnb.sv-comp18-violation-witness.ReachSafety-BitVectors uautomizer-validate-violation-witnesses-cpa-bam-bnb.sv-comp18-violation-witness.ReachSafety-BitVectors cpa-witness2test-validate-violation-witnesses-cpa-bam-bnb.sv-comp18-violation-witness.ReachSafety-BitVectors fshell-witness2test-validate-violation-witnesses-cpa-bam-bnb.sv-comp18-violation-witness.ReachSafety-BitVectors cpa-seq-validate-correctness-witnesses-cpa-bam-bnb.sv-comp18-correctness-witness.ReachSafety-BitVectors uautomizer-validate-correctness-witnesses-cpa-bam-bnb.sv-comp18-correctness-witness.ReachSafety-BitVectors