Tool 2LS 0.6.0 CPAchecker 1.6.1-svn 26773 ULTIMATE Automizer 0.1.23-3204b741 CPA-witness2test 1.6.1-svn 26773 CProver witness2test 0.1 CPAchecker 1.6.1-svn 26773 ULTIMATE Automizer 0.1.23-3204b741
Limits timelimit: 900 s, memlimit: 15000 MB, CPU core limit: 8 timelimit: 90 s, memlimit: 7000 MB, CPU core limit: 2 timelimit: 900 s, memlimit: 7000 MB, CPU core limit: 2
Host apollon*
OS Linux 4.4.0-101-generic
System CPU: Intel Xeon E3-1230 v5 @ 3.40 GHz, cores: 8, frequency: 3.8 GHz, Turbo Boost: disabled; RAM: 33553 MB CPU: Intel Xeon E3-1230 v5 @ 3.40 GHz, cores: [8; 4], frequency: 3.8 GHz, Turbo Boost: disabled; RAM: [33553 MB; 33554 MB]
Date of execution 2017-11-30 11:20:26 CET 2017-12-01 07:32:03 CET 2017-12-01 08:01:50 CET 2017-12-01 08:11:41 CET 2017-12-01 08:15:34 CET 2017-12-01 04:23:32 CET 2017-12-01 07:36:49 CET
Run set 2ls.sv-comp18.ReachSafety-BitVectors cpa-seq-validate-violation-witnesses-2ls.sv-comp18-violation-witness.ReachSafety-BitVectors uautomizer-validate-violation-witnesses-2ls.sv-comp18-violation-witness.ReachSafety-BitVectors cpa-witness2test-validate-violation-witnesses-2ls.sv-comp18-violation-witness.ReachSafety-BitVectors fshell-witness2test-validate-violation-witnesses-2ls.sv-comp18-violation-witness.ReachSafety-BitVectors cpa-seq-validate-correctness-witnesses-2ls.sv-comp18-correctness-witness.ReachSafety-BitVectors uautomizer-validate-correctness-witnesses-2ls.sv-comp18-correctness-witness.ReachSafety-BitVectors
Options --graphml-witness witness.graphml -witnessValidation -setprop witness.checkProgramHash=false -heap 5000m -benchmark -witness ../../results-verified/2ls.2017-11-30_1120.logfiles/sv-comp18.${inputfile_name}.files/witness.graphml -setprop cpa.predicate.memoryAllocationsAlwaysSucceed=true -setprop cpa.smg.memoryAllocationFunctions=malloc,__kmalloc,kmalloc,kzalloc,kzalloc_node,ldv_zalloc,ldv_malloc -setprop cpa.smg.arrayAllocationFunctions=calloc,kmalloc_array,kcalloc -setprop cpa.smg.zeroingMemoryAllocation=calloc,kzalloc,kcalloc,kzalloc_node,ldv_zalloc -setprop cpa.smg.deallocationFunctions=free,kfree,kfree_const --full-output --validate ../../results-verified/2ls.2017-11-30_1120.logfiles/sv-comp18.${inputfile_name}.files/witness.graphml -witness2test -setprop witness.checkProgramHash=false -heap 5000m -benchmark -witness ../../results-verified/2ls.2017-11-30_1120.logfiles/sv-comp18.${inputfile_name}.files/witness.graphml -setprop analysis.summaryEdges=true -setprop cpa.callstack.skipVoidRecursion=true -setprop cpa.callstack.skipFunctionPointerRecursion=true --graphml-witness ../../results-verified/2ls.2017-11-30_1120.logfiles/sv-comp18.${inputfile_name}.files/witness.graphml -witnessValidation -setprop witness.checkProgramHash=false -heap 5000m -benchmark -witness ../../results-verified/2ls.2017-11-30_1120.logfiles/sv-comp18.${inputfile_name}.files/witness.graphml -setprop cpa.predicate.memoryAllocationsAlwaysSucceed=true --full-output --validate ../../results-verified/2ls.2017-11-30_1120.logfiles/sv-comp18.${inputfile_name}.files/witness.graphml
sv-benchmarks/c/ status score witness inspect witness cpu (s) mem (MB) energy (J) status score witness inspect witness cpu (s) mem (MB) energy status score witness inspect witness cpu (s) mem (MB) energy status score witness inspect witness cpu (s) mem (MB) energy status score witness inspect witness cpu (s) mem (MB) energy status score witness inspect witness cpu (s) mem (MB) energy status score witness inspect witness cpu (s) mem (MB) energy
bitvector/byte_add_false-unreach-call_true-no-overflow_true-termination.i 1 .32  28 3.8  1 3.7  270 -32 20     530   0 3.9  220 1 .70   18    - -
bitvector/sum02_false-unreach-call_true-no-overflow.i 0 900     1400 10000    0 .54 43 0 .021 4.8 0 .90 49 0 .0015 .27 - -
bitvector/byte_add_1_true-unreach-call_true-no-overflow_true-termination.i 2 .33  29 4.3  - - - - 2 8.2  370 0 960     1100  
bitvector/byte_add_2_true-unreach-call_true-no-overflow_true-termination.i 2 .34  31 3.7  - - - - 2 8.6  310 0 960     1100  
bitvector/gcd_1_true-unreach-call_true-no-overflow.i 2 .25  27 2.6  - - - - 2 9.7  310 -16 5.3   260  
bitvector/gcd_2_true-unreach-call_true-no-overflow.i 2 .76  39 9.0  - - - - 2 160    460 0 960     630  
bitvector/gcd_3_true-unreach-call_true-no-overflow.i 2 .64  40 7.4  - - - - 2 160    480 0 960     4300  
bitvector/gcd_4_true-unreach-call_true-no-overflow_true-termination.i 2 .56  33 6.0  - - - - 2 7.8  320 2 45     570  
bitvector/interleave_bits_true-unreach-call_true-no-overflow.i 2 .48  55 5.6  - - - - 2 6.6  310 2 170     610  
bitvector/jain_1_true-unreach-call_true-no-overflow_false-termination.i 0 900     1500 10000    - - - - 0 .69 41 0 .030 5.0
bitvector/jain_2_true-unreach-call_true-no-overflow_false-termination.i 0 900     1500 11000    - - - - 0 .53 42 0 .019 5.0
bitvector/jain_4_true-unreach-call_true-no-overflow_false-termination.i 0 900     1900 11000    - - - - 0 .54 44 0 .019 5.0
bitvector/jain_5_true-unreach-call_true-no-overflow.i 0 900     1400 13000    - - - - 0 .54 42 0 .020 4.9
bitvector/jain_6_true-unreach-call_true-no-overflow_false-termination.i 0 900     1800 10000    - - - - 0 .69 42 0 .018 4.9
bitvector/jain_7_true-unreach-call_true-no-overflow_false-termination.i 0 900     1700 11000    - - - - 0 .55 46 0 .018 4.8
bitvector/modulus_true-unreach-call_true-no-overflow.i 2 .63  39 8.9  - - - - 2 13    330 2 16     330  
bitvector/num_conversion_1_true-unreach-call_true-no-overflow.i 2 .12  24 1.2  - - - - 2 5.2  270 2 54     640  
bitvector/num_conversion_2_true-unreach-call_true-no-overflow.i 2 .17  24 1.2  - - - - 2 4.9  280 0 960     1100  
bitvector/parity_true-unreach-call_true-no-overflow.i 2 2.7   44 30    - - - - 2 26    380 0 960     1000  
bitvector/sum02_true-unreach-call_true-no-overflow.i 0 900     1500 12000    - - - - 0 .57 41 0 .019 4.9
bitvector/s3_clnt_1_false-unreach-call_true-no-overflow.BV.c.cil.c 1 9.4   220 77    -32 4.6  270 -32 6.4   320   0 4.0  220 1 .81   20    - -
bitvector/s3_clnt_2_false-unreach-call_true-no-overflow.BV.c.cil.c 1 7.3   240 83    -32 4.9  270 -32 9.4   350   0 4.7  230 1 .94   20    - -
bitvector/s3_clnt_3_false-unreach-call_true-no-overflow.BV.c.cil.c 1 7.3   150 67    -32 4.6  270 -32 6.8   300   0 4.3  220 1 .72   19    - -
bitvector/s3_clnt_1_true-unreach-call_true-no-overflow.BV.c.cil.c 2 46     320 410    - - - - 2 81    810 2 40     760  
bitvector/s3_clnt_2_true-unreach-call_true-no-overflow.BV.c.cil.c 2 8.0   280 95    - - - - 2 19    480 2 48     880  
bitvector/s3_clnt_3_true-unreach-call_true-no-overflow.BV.c.cil.c 2 9.1   250 84    - - - - 2 16    410 2 34     800  
bitvector/s3_srvr_1_alt_true-unreach-call_true-no-overflow.BV.c.cil.c 0 900     810 9700    - - - - 0 .57 42 0 .048 5.0
bitvector/s3_srvr_1_true-unreach-call_true-no-overflow.BV.c.cil.c 0 900     7600 9900    - - - - 0 .70 43 0 .019 4.8
bitvector/s3_srvr_2_alt_true-unreach-call_true-no-overflow_false-termination.BV.c.cil.c 0 900     6700 10000    - - - - 0 .66 42 0 .023 4.8
bitvector/s3_srvr_2_true-unreach-call_true-no-overflow_false-termination.BV.c.cil.c 0 900     6800 11000    - - - - 0 .58 41 0 .019 4.9
bitvector/s3_srvr_3_alt_true-unreach-call_true-no-overflow.BV.c.cil.c 0 900     7100 10000    - - - - 0 .66 44 0 .020 4.8
bitvector/s3_srvr_3_true-unreach-call_true-no-overflow.BV.c.cil.c 0 900     7000 9700    - - - - 0 .65 45 0 .020 4.9
bitvector/soft_float_1_true-unreach-call_true-no-overflow_true-termination.c.cil.c 2 .22  28 2.0  - - - - 0 900    6100 2 110     780  
bitvector/soft_float_2_true-unreach-call_true-no-overflow_true-termination.c.cil.c 2 .17  29 1.4  - - - - 0 900    6200 2 50     700  
bitvector/soft_float_3_true-unreach-call_true-no-overflow_true-termination.c.cil.c 1 4.0   160 48    - - - - 0 920    6300 0 960     770  
bitvector/soft_float_4_true-unreach-call_true-no-overflow_true-termination.c.cil.c 2 1.1   36 12    - - - - 2 220    640 2 310     820  
bitvector/soft_float_5_true-unreach-call_true-no-overflow_true-termination.c.cil.c 2 .17  28 1.3  - - - - 0 900    6100 2 24     620  
bitvector-regression/implicitfloatconversion_false-unreach-call_true-termination.c 1 .090 22 1.2  -32 2.8  260 -32 5.0   220   0 2.7  210 1 .58   18    - -
bitvector-regression/implicitunsignedconversion_false-unreach-call_true-termination.c 1 .099 22 .83 -32 2.8  260 -32 5.2   220   0 3.6  190 1 .76   18    - -
bitvector-regression/integerpromotion_false-unreach-call_true-termination.c 1 .12  22 .82 -32 3.1  260 -32 4.6   210   0 3.1  210 1 .66   18    - -
bitvector-regression/recHanoi03_false-unreach-call_true-termination.c 0 .11  22 .64 0 .50 41 0 .020 5.0 0 .92 48 0 .0012 .33 - -
bitvector-regression/signextension2_false-unreach-call_true-termination.c 1 .13  22 .83 -32 3.0  260 -32 4.8   210   0 3.3  180 1 .71   18    - -
bitvector-regression/signextension_false-unreach-call_true-termination.c 1 .12  22 .77 -32 2.7  260 -32 4.8   210   0 3.3  210 1 .57   18    - -
bitvector-regression/implicitunsignedconversion_true-unreach-call_true-termination.c 2 .10  22 .82 - - - - 2 3.3  250 2 6.0   250  
bitvector-regression/integerpromotion_true-unreach-call_true-termination.c 2 .12  22 .84 - - - - 2 3.1  250 2 9.2   240  
bitvector-regression/signextension2_true-unreach-call_true-termination.c 2 .12  22 .74 - - - - 2 3.0  250 2 4.9   260  
bitvector-regression/signextension_true-unreach-call_true-termination.c 2 .12  22 .76 - - - - 2 4.2  250 2 5.4   250  
bitvector-loops/diamond_false-unreach-call2.i 1 .12  24 1.1  1 3.4  260 1 5.2   270   0 3.3  210 1 .60   19    - -
bitvector-loops/overflow_false-unreach-call1.i 0 900     1300 11000    0 .54 43 0 .023 4.9 0 .91 49 0 .0018 .26 - -
bitvector-loops/verisec_sendmail__tTflag_arr_one_loop_false-unreach-call_true-termination.i 1 .54  37 6.0  1 4.5  290 0 49     7000   0 3.7  210 1 .65   19    - -
sv-benchmarks/c/ status score witness inspect witness cpu (s) mem (MB) energy (J) status score witness inspect witness cpu (s) mem (MB) energy status score witness inspect witness cpu (s) mem (MB) energy status score witness inspect witness cpu (s) mem (MB) energy status score witness inspect witness cpu (s) mem (MB) energy status score witness inspect witness cpu (s) mem (MB) energy status score witness inspect witness cpu (s) mem (MB) energy
total 50 56 14000   52000 160000 14 -253 42 3000 14 -287 120   9800 14 0 43 2500 14 11 7.7 210 36 38 4400 32000 36 14 7700   19000
    correct results 33 55 98   2200 930 3 3 12 810 1 1 5.2 270 0 11 11 7.7 210 19 38 760 7200 15 30 920   8500
        correct true 22 44 72   1400 690 0 0 0 0 19 38 760 7200 15 30 920   8500
        correct false 11 11 26   800 240 3 3 12 810 1 1 5.2 270 0 11 11 7.7 210 0 0
    correct-unconfimed results 1 1 4.0 160 48 0 0 0 0 0 0
        correct-unconfirmed true 1 1 4.0 160 48 0 0 0 0 0 0
        correct-unconfirmed false 0 0 0 0 0 0 0
    incorrect results 0 8 -256 28 2100 9 -288 67   2600 0 0 0 1 -16 5.3 260
        incorrect true 0 8 -256 28 2100 9 -288 67   2600 0 0 0 0
        incorrect false 0 0 0 0 0 0 1 -16 5.3 260
score (50 tasks, max score: 86) 56 -253 -287 0 11 38 14
Run set 2ls.sv-comp18.ReachSafety-BitVectors cpa-seq-validate-violation-witnesses-2ls.sv-comp18-violation-witness.ReachSafety-BitVectors uautomizer-validate-violation-witnesses-2ls.sv-comp18-violation-witness.ReachSafety-BitVectors cpa-witness2test-validate-violation-witnesses-2ls.sv-comp18-violation-witness.ReachSafety-BitVectors fshell-witness2test-validate-violation-witnesses-2ls.sv-comp18-violation-witness.ReachSafety-BitVectors cpa-seq-validate-correctness-witnesses-2ls.sv-comp18-correctness-witness.ReachSafety-BitVectors uautomizer-validate-correctness-witnesses-2ls.sv-comp18-correctness-witness.ReachSafety-BitVectors