Tool ULTIMATE Automizer f7c3ed31
Limits timelimit: 900 s, memlimit: 15000 MB, CPU core limit: 8
Host apollon*
OS Linux 4.4.0-59-generic
System CPU: Intel Xeon E3-1230 v5 @ 3.40 GHz, cores: 8, frequency: 3.8 GHz, Turbo Boost: disabled; RAM: 33553 MB
Date of execution 2017-01-13 12:41:58 CET [[ 2017-01-15 02:09:41 CET ]] [[ 2017-01-15 04:03:21 CET ]] [[ 2017-01-15 02:31:54 CET ]] [[ 2017-01-15 04:27:36 CET ]]
Run set sv-comp17.ReachSafety-BitVectors
Options [[ -witnessValidation -setprop witness.checkProgramHash=false -disable-java-assertions -heap 10000m -witness ../../results-verified/uautomizer.2017-01-13_1241.logfiles/sv-comp17.${inputfile_name}.files/witness.graphml ]][[ --validate ../../results-verified/uautomizer.2017-01-13_1241.logfiles/sv-comp17.${inputfile_name}.files/witness.graphml ]][[ -witnessValidation -setprop witness.checkProgramHash=false -disable-java-assertions -heap 10000m -witness ../../results-verified/uautomizer.2017-01-13_1241.logfiles/sv-comp17.${inputfile_name}.files/witness.graphml ]][[ --validate ../../results-verified/uautomizer.2017-01-13_1241.logfiles/sv-comp17.${inputfile_name}.files/witness.graphml ]]
../../sv-benchmarks/c/ verifier status score witness inspect witness cpu (s) wall (s) energy (J) mem (MB) blkio-w (MB) blkio-r (MB) validator cpachecker violation t<90s status cpu (s) wall (s) energy (J) mem (MB) validator uautomizer violation t<90s status cpu (s) wall (s) energy (J) mem (MB) validator cpachecker correctness t<900s status cpu (s) wall (s) energy (J) mem (MB) validator uautomizer correctness t<900s status cpu (s) wall (s) energy (J) mem (MB)
bitvector/byte_add_false-unreach-call_true-no-overflow.i 1 55   24   540 750 2.6 0      26    14    250   930 35   19   300 530
bitvector/sum02_false-unreach-call_true-no-overflow.i 0 900   900   11000 340 2.3 0      .53 .35 13   39 6.0 3.2 120 310
bitvector/byte_add_1_true-unreach-call_true-no-overflow.i 0 900   800   11000 4100 2.5 0      .66 .42 9.2 41 5.9 3.2 120 300
bitvector/byte_add_2_true-unreach-call_true-no-overflow.i 2 580   510   6800 1400 2.6 0      9.2  5.0  190   340 400   350   5100 1600
bitvector/gcd_1_true-unreach-call_true-no-overflow.i 0 900   890   11000 530 2.3 0      .54 .36 8.6 39 6.5 3.4 130 300
bitvector/gcd_2_true-unreach-call_true-no-overflow.i 0 900   890   11000 730 2.3 0      .54 .34 9.2 40 5.4 2.9 100 290
bitvector/gcd_3_true-unreach-call_true-no-overflow.i 0 900   890   11000 560 2.3 0      .50 .32 11   40 5.6 3.0 87 290
bitvector/gcd_4_true-unreach-call_true-no-overflow.i 0 900   880   11000 670 2.3 0      .65 .41 9.1 40 6.6 3.5 130 300
bitvector/interleave_bits_true-unreach-call_true-no-overflow.i 2 120   98   1200 1700 2.6 0      8.1  5.0  150   350 80   63   990 640
bitvector/jain_1_true-unreach-call_true-no-overflow.i 2 6.7 2.0 55 340 2.5 0      900    900    17000   2500 8.3 4.5 150 330
bitvector/jain_2_true-unreach-call_true-no-overflow.i 2 7.2 2.0 56 340 2.5 0      900    900    24000   3800 7.8 4.2 100 320
bitvector/jain_4_true-unreach-call_true-no-overflow.i 2 5.7 1.9 49 330 2.5 0      900    900    19000   1600 12   7.4 150 360
bitvector/jain_5_true-unreach-call_true-no-overflow.i 0 900   760   13000 2200 2.3 0      .52 .34 12   40 5.6 3.0 83 310
bitvector/jain_6_true-unreach-call_true-no-overflow.i 2 5.9 2.0 48 330 2.5 0      900    900    26000   1700 8.6 4.7 170 320
bitvector/jain_7_true-unreach-call_true-no-overflow.i 2 5.9 2.0 50 320 2.5 0      900    900    19000   690 43   38   640 370
bitvector/modulus_true-unreach-call_true-no-overflow.i 0 29   25   420 330 2.5 0      .76 .48 9.1 44 6.0 3.2 110 290
bitvector/num_conversion_1_true-unreach-call_true-no-overflow.i 2 270   250   3800 2300 2.5 0      4.6  2.6  89   280 60   48   960 530
bitvector/num_conversion_2_true-unreach-call_true-no-overflow.i 0 900   860   11000 880 2.5 0      .47 .30 9.3 39 5.6 3.0 100 290
bitvector/parity_true-unreach-call_true-no-overflow.i 0 900   880   11000 1000 2.5 0      .56 .37 9.1 39 6.0 3.2 130 300
bitvector/sum02_true-unreach-call_true-no-overflow.i 0 900   890   12000 510 2.3 0      .71 .44 8.8 42 6.2 3.2 120 290
bitvector/s3_clnt_1_false-unreach-call_true-no-overflow.BV.c.cil.c 1 24   6.9 200 570 2.9 0      6.5  3.4  80   300 22   12   190 520
bitvector/s3_clnt_2_false-unreach-call_true-no-overflow.BV.c.cil.c 1 28   7.7 220 720 3.0 0      7.0  3.7  120   300 36   19   380 600
bitvector/s3_clnt_3_false-unreach-call_true-no-overflow.BV.c.cil.c 1 22   6.4 170 560 2.8 0      6.4  3.4  68   290 25   13   400 510
bitvector/s3_clnt_1_true-unreach-call_true-no-overflow.BV.c.cil.c 2 35   9.8 280 840 2.8 0      63    53    1100   950 45   25   430 810
bitvector/s3_clnt_2_true-unreach-call_true-no-overflow.BV.c.cil.c 2 42   13   360 1100 2.7 0      18    11    280   600 53   29   600 1000
bitvector/s3_clnt_3_true-unreach-call_true-no-overflow.BV.c.cil.c 2 25   6.4 190 1100 2.7 0      21    12    270   570 120   75   1300 7000
bitvector/s3_srvr_1_alt_true-unreach-call_true-no-overflow.BV.c.cil.c 0 900   870   13000 2400 2.3 0      .65 .41 8.0 39 6.8 3.5 100 310
bitvector/s3_srvr_1_true-unreach-call_true-no-overflow.BV.c.cil.c 2 47   17   460 1900 2.7 0      910    900    16000   4900 52   28   670 1100
bitvector/s3_srvr_2_alt_true-unreach-call_true-no-overflow.BV.c.cil.c 2 39   12   340 1500 2.7 0      910    890    15000   4200 41   22   460 1100
bitvector/s3_srvr_2_true-unreach-call_true-no-overflow.BV.c.cil.c 2 38   12   290 1600 2.7 0      910    890    14000   4100 42   22   420 1100
bitvector/s3_srvr_3_alt_true-unreach-call_true-no-overflow.BV.c.cil.c 2 36   11   300 1400 2.7 0      910    900    20000   5300 44   24   430 1100
bitvector/s3_srvr_3_true-unreach-call_true-no-overflow.BV.c.cil.c 2 36   11   310 1500 2.7 0      910    900    16000   5400 46   24   570 1000
bitvector/soft_float_1_true-unreach-call_true-no-overflow.c.cil.c 0 160   130   1900 890 2.5 0      .58 .37 13   42 5.5 3.0 95 290
bitvector/soft_float_2_true-unreach-call_true-no-overflow.c.cil.c 2 220   200   2500 1000 2.5 0      800    730    20000   7000 80   66   1200 950
bitvector/soft_float_3_true-unreach-call_true-no-overflow.c.cil.c 0 900   870   10000 1600 2.5 0      .63 .41 7.5 40 7.3 3.8 90 300
bitvector/soft_float_4_true-unreach-call_true-no-overflow.c.cil.c 2 510   470   5400 1000 2.6 0      380    370    7900   770 290   260   3500 1000
bitvector/soft_float_5_true-unreach-call_true-no-overflow.c.cil.c 2 15   4.4 110 610 2.6 0      750    670    24000   7000 20   11   260 540
bitvector-regression/implicitfloatconversion_false-unreach-call.c 1 9.1 3.0 69 320 2.6 0      4.4  2.5  50   270 11   5.8 150 310
bitvector-regression/implicitunsignedconversion_false-unreach-call.c 1 5.4 1.8 45 320 2.5 0      3.4  1.9  47   270 6.8 3.6 100 310
bitvector-regression/integerpromotion_false-unreach-call.c 1 8.9 3.0 74 320 2.6 0      3.5  2.0  51   270 12   6.2 170 330
bitvector-regression/recHanoi03_false-unreach-call.c 0 87   62   1200 880 2.6 0      95    81    1500   3800 7.9 4.2 110 340
bitvector-regression/signextension2_false-unreach-call.c 1 5.8 1.9 43 320 2.5 0      3.6  2.0  61   270 6.9 3.7 120 310
bitvector-regression/signextension_false-unreach-call.c 1 6.7 1.9 51 330 2.5 0      3.6  2.0  59   260 7.1 3.8 140 320
bitvector-regression/implicitunsignedconversion_true-unreach-call.c 2 5.6 1.9 44 330 2.5 0      4.2  2.4  44   260 7.9 4.2 160 330
bitvector-regression/integerpromotion_true-unreach-call.c 2 9.0 3.1 75 310 2.6 0      4.1  2.3  39   260 12   6.3 170 310
bitvector-regression/signextension2_true-unreach-call.c 2 5.7 1.8 49 320 2.5 0      4.0  2.3  51   250 7.5 4.0 150 320
bitvector-regression/signextension_true-unreach-call.c 2 6.1 1.9 43 330 2.5 0      4.0  2.2  63   270 7.7 4.1 120 320
bitvector-loops/diamond_false-unreach-call2.i 1 8.1 2.7 61 370 2.5 0      4.2  2.3  53   290 8.2 4.4 150 360
bitvector-loops/overflow_false-unreach-call1.i 0 900   750   15000 1500 2.3 0      .50 .31 9.2 43 5.4 2.9 100 290
bitvector-loops/verisec_sendmail__tTflag_arr_one_loop_false-unreach-call.i 0 160   150   2000 740 2.5 .0082 4.2  2.3  67   280 72   43   850 7000
../../sv-benchmarks/c/ verifier status score witness inspect witness cpu (s) wall (s) energy (J) mem (MB) blkio-w (MB) blkio-r (MB) validator cpachecker violation t<90s status cpu (s) wall (s) energy (J) mem (MB) validator uautomizer violation t<90s status cpu (s) wall (s) energy (J) mem (MB) validator cpachecker correctness t<900s status cpu (s) wall (s) energy (J) mem (MB) validator uautomizer correctness t<900s status cpu (s) wall (s) energy (J) mem (MB)
total 50 56 14000 13000 180000 46000 130   .0082 50 170 120 2500 7600   50 260 140 3300 12000   50 11000 11000 240000 54000   50 1600 1200 20000 26000  
    correct results 33 56 2200 1700 24000 26000 86   0      10 69 38 840 3500   10 170 90 2100 4100   11 11000 11000 240000 53000   22 1500 1100 19000 23000  
        correct true 23 46 2100 1600 23000 22000 60   0      4 0 0 0 0   0 0 0 0 0   11 11000 11000 240000 53000   22 1500 1100 19000 23000  
        correct false 10 10 170 60 1500 4600 26   0      6 69 38 840 3500   10 170 90 2100 4100   0 0 0 0 0   0 0 0 0 0  
    correct-unconfimed results 2 0 250 210 3200 1600 5.1 .0082 1 99 84 1600 4100   1 79 47 960 7300   0 0 0 0 0   0 0 0 0 0  
        correct-unconfirmed true 0
        correct-unconfirmed false 2 0 250 210 3200 1600 5.1 .0082 0 99 84 1600 4100   0 79 47 960 7300   0 0 0 0 0   0 0 0 0 0  
    incorrect results 0
        incorrect true 0
        incorrect false 0
score (50 tasks, max score: 86) 56
Run set sv-comp17.ReachSafety-BitVectors