Tool SMACK+Corral 1.5.2
Limits timelimit: 900 s, memlimit: 15000 MB, CPU core limit: 8
Host [zeus01; zeus02; zeus03; zeus04; zeus05; zeus06; zeus07; zeus08; zeus09; zeus10; zeus11; zeus12; zeus13; zeus14; zeus15; zeus16; zeus17; zeus18; zeus19; zeus20; zeus21; zeus22; zeus23; zeus24]
OS Linux 4.2.0-23-generic
System CPU: Intel Xeon E5-2650 v2 @ 2.60 GHz, cores: 32, frequency: 3.4 GHz; RAM: 135149 MB
Date of execution 2016-01-07 09:05:16 CET [[ 2016-01-15 09:34:34 CET ]] [[ 2016-01-15 22:36:10 CET ]]
Run set sv-comp16.BitVectorsReach
Options -w error-witness.graphml [[ -witness-check -disable-java-assertions -heap 10000m -setprop cpa.arg.errorPath.graphml=error-witness.graphml -spec ../../results-verified/smack.2016-01-07_0905.logfiles/sv-comp16.${inputfile_name}.files/error-witness.graphml ]][[ ../../results-verified/smack.2016-01-07_0905.logfiles/sv-comp16.${inputfile_name}.files/error-witness.graphml ]]
../../sv-benchmarks/c/ status cputime (s) walltime (s) memUsage (MB) witness wit1_status wit1_cputime (s) wit1_walltime (s) wit1_memUsage (MB) wit2_status wit2_cputime (s) wit2_walltime (s) wit2_memUsage (MB)
bitvector/byte_add_false-unreach-call.i 6.8 6.7 140 6.9 3.9 270 69 42   560
bitvector/byte_add_1_true-unreach-call.i 23   22   160
bitvector/byte_add_2_true-unreach-call.i 24   24   160
bitvector/gcd_1_true-unreach-call.i 2.9 2.9 73
bitvector/gcd_2_true-unreach-call.i 2.9 2.9 71
bitvector/gcd_3_true-unreach-call.i 2.8 2.8 70
bitvector/gcd_4_true-unreach-call.i 3.4 3.4 75
bitvector/interleave_bits_true-unreach-call.i 2.2 2.3 73
bitvector/jain_1_true-unreach-call.i 880   880   110
bitvector/jain_2_true-unreach-call.i 880   880   100
bitvector/jain_4_true-unreach-call.i 880   930   140
bitvector/jain_5_true-unreach-call.i 900   900   700
bitvector/jain_6_true-unreach-call.i 880   930   110
bitvector/jain_7_true-unreach-call.i 880   930   94
bitvector/modulus_true-unreach-call.i 47   47   160
bitvector/num_conversion_1_true-unreach-call.i 2.6 2.6 64
bitvector/num_conversion_2_true-unreach-call.i 2.6 2.6 67
bitvector/parity_true-unreach-call.i 880   880   290
bitvector/sum02_true-unreach-call.i 880   880   390
bitvector/s3_clnt_1_false-unreach-call.BV.c.cil.c 17   17   210 91   69   3700 14 7.8 350
bitvector/s3_clnt_2_false-unreach-call.BV.c.cil.c 40   39   240 91   68   2800 15 11   350
bitvector/s3_clnt_3_false-unreach-call.BV.c.cil.c 11   11   180 91   69   3000 15 12   340
bitvector/s3_clnt_1_true-unreach-call.BV.c.cil.c 210   210   320
bitvector/s3_clnt_2_true-unreach-call.BV.c.cil.c 170   170   290
bitvector/s3_clnt_3_true-unreach-call.BV.c.cil.c 180   180   300
bitvector/s3_srvr_1_alt_true-unreach-call.BV.c.cil.c 880   880   430
bitvector/s3_srvr_1_true-unreach-call.BV.c.cil.c 880   880   530
bitvector/s3_srvr_2_alt_true-unreach-call.BV.c.cil.c 880   880   520
bitvector/s3_srvr_2_true-unreach-call.BV.c.cil.c 880   880   560
bitvector/s3_srvr_3_alt_true-unreach-call.BV.c.cil.c 880   880   650
bitvector/s3_srvr_3_true-unreach-call.BV.c.cil.c 880   880   610
bitvector/soft_float_1_true-unreach-call.c.cil.c 3.4 3.4 88
bitvector/soft_float_2_true-unreach-call.c.cil.c 3.2 3.2 87
bitvector/soft_float_3_true-unreach-call.c.cil.c 21   21   130
bitvector/soft_float_4_true-unreach-call.c.cil.c 12   12   88
bitvector/soft_float_5_true-unreach-call.c.cil.c 2.7 2.7 87
bitvector-regression/implicitfloatconversion_false-unreach-call.i 2.9 2.9 68 4.6 2.7 220 11 6.1 320
bitvector-regression/implicitunsignedconversion_false-unreach-call.i 2.8 2.8 72 4.4 2.6 220 11 7.0 320
bitvector-regression/integerpromotion_false-unreach-call.i 3.0 3.0 72 7.0 3.9 340 22 14   390
bitvector-regression/signextension2_false-unreach-call.i 3.1 3.1 70 7.1 4.0 330 12 7.9 350
bitvector-regression/signextension_false-unreach-call.i 3.0 2.9 74 7.3 4.1 330 11 6.5 330
bitvector-regression/implicitunsignedconversion_true-unreach-call.i 2.5 2.5 61
bitvector-regression/integerpromotion_true-unreach-call.i 2.0 2.0 65
bitvector-regression/signextension2_true-unreach-call.i 2.7 2.8 67
bitvector-regression/signextension_true-unreach-call.i 2.8 2.8 67
bitvector-loops/diamond_false-unreach-call2.i 3.6 3.6 85 15   8.3 400 13 8.5 340
bitvector-loops/overflow_false-unreach-call1.i 890   890   830
bitvector-loops/verisec_sendmail__tTflag_arr_one_loop_false-unreach-call.i 7.0 6.9 93 5.4 3.1 230 20 12   410
../../sv-benchmarks/c/ status cputime (s) walltime (s) memUsage (MB) witness wit1_status wit1_cputime (s) wit1_walltime (s) wit1_memUsage (MB) wit2_status wit2_cputime (s) wit2_walltime (s) wit2_memUsage (MB)
total tasks 48 14000 14000 10000 48 330   240   12000   48 210   130   4000  
    correct results 39 9600 9600 7400 7 53   30   2100   6 150   92   2600  
        correct true 32 9600 9500 6800 2 0   0   0   0 0   0   0  
        correct false 7 25 25 580 5 53   30   2100   6 150   92   2600  
    incorrect results 0
        incorrect true 0
        incorrect false 0
score (48 tasks, max score: 84) 71
Run set sv-comp16.BitVectorsReach