Tool LCTD
Limits timelimit: 900 s, memlimit: 15000 MB, CPU core limit: 8
Host [zeus01; zeus02; zeus03; zeus04; zeus05; zeus06; zeus07; zeus08; zeus09; zeus10; zeus11; zeus13; zeus14; zeus15; zeus16; zeus17; zeus18; zeus19; zeus20; zeus21; zeus22; zeus23; zeus24]
OS Linux 4.2.0-23-generic
System CPU: Intel Xeon E5-2650 v2 @ 2.60 GHz, cores: 32, frequency: 3.4 GHz; RAM: 135149 MB
Date of execution 2016-01-07 07:06:46 CET [[ 2016-01-15 09:15:21 CET ]] [[ 2016-01-15 22:25:37 CET ]]
Run set sv-comp16
Options [[ -witness-check -disable-java-assertions -heap 10000m -setprop cpa.arg.errorPath.graphml=error-witness.graphml -spec ../../results-verified/lctd.2016-01-07_0706.logfiles/sv-comp16.${inputfile_name}.files/error-witness.graphml ]][[ ../../results-verified/lctd.2016-01-07_0706.logfiles/sv-comp16.${inputfile_name}.files/error-witness.graphml ]]
../../sv-benchmarks/c/ status cputime (s) walltime (s) memUsage (MB) witness wit1_status wit1_cputime (s) wit1_walltime (s) wit1_memUsage (MB) wit2_status wit2_cputime (s) wit2_walltime (s) wit2_memUsage (MB)
bitvector/byte_add_false-unreach-call.i 9.5   8.5   280   3.6 2.1 170 .028 .033 5.0
bitvector/byte_add_1_true-unreach-call.i 1.6   6.4   38  
bitvector/byte_add_2_true-unreach-call.i 7.3   6.2   150  
bitvector/gcd_1_true-unreach-call.i 1.1   .90  68  
bitvector/gcd_2_true-unreach-call.i 1.3   1.1   85  
bitvector/gcd_3_true-unreach-call.i .50  5.4   37  
bitvector/gcd_4_true-unreach-call.i .55  5.4   41  
bitvector/interleave_bits_true-unreach-call.i .52  5.4   41  
bitvector/jain_1_true-unreach-call.i .88  .84  55  
bitvector/jain_2_true-unreach-call.i .60  5.4   45  
bitvector/jain_4_true-unreach-call.i .44  5.4   34  
bitvector/jain_5_true-unreach-call.i .90  .85  52  
bitvector/jain_6_true-unreach-call.i 1.0   .81  76  
bitvector/jain_7_true-unreach-call.i .78  5.5   47  
bitvector/modulus_true-unreach-call.i .59  5.5   42  
bitvector/num_conversion_1_true-unreach-call.i .50  5.3   38  
bitvector/num_conversion_2_true-unreach-call.i .32  5.4   19  
bitvector/parity_true-unreach-call.i 1.4   1.4   56  
bitvector/sum02_true-unreach-call.i .59  5.5   36  
bitvector/s3_clnt_1_false-unreach-call.BV.c.cil.c 6.9   5.9   130  
bitvector/s3_clnt_2_false-unreach-call.BV.c.cil.c 6.5   5.6   140  
bitvector/s3_clnt_3_false-unreach-call.BV.c.cil.c 1.0   5.9   37  
bitvector/s3_clnt_1_true-unreach-call.BV.c.cil.c .98  5.9   40  
bitvector/s3_clnt_2_true-unreach-call.BV.c.cil.c .62  5.7   19  
bitvector/s3_clnt_3_true-unreach-call.BV.c.cil.c .91  5.9   20  
bitvector/s3_srvr_1_alt_true-unreach-call.BV.c.cil.c 1.1   6.0   44  
bitvector/s3_srvr_1_true-unreach-call.BV.c.cil.c .76  5.8   19  
bitvector/s3_srvr_2_alt_true-unreach-call.BV.c.cil.c .94  5.9   27  
bitvector/s3_srvr_2_true-unreach-call.BV.c.cil.c 1.2   6.0   40  
bitvector/s3_srvr_3_alt_true-unreach-call.BV.c.cil.c .87  5.9   19  
bitvector/s3_srvr_3_true-unreach-call.BV.c.cil.c .94  5.8   41  
bitvector/soft_float_1_true-unreach-call.c.cil.c 35     40     42  
bitvector/soft_float_2_true-unreach-call.c.cil.c 1.3   6.1   39  
bitvector/soft_float_3_true-unreach-call.c.cil.c 1.9   1.6   77  
bitvector/soft_float_4_true-unreach-call.c.cil.c 1.4   1.2   78  
bitvector/soft_float_5_true-unreach-call.c.cil.c 1.6   6.2   69  
bitvector-regression/implicitfloatconversion_false-unreach-call.i .64  5.4   40  
bitvector-regression/implicitunsignedconversion_false-unreach-call.i .72  5.4   38  
bitvector-regression/integerpromotion_false-unreach-call.i .67  5.5   37  
bitvector-regression/signextension2_false-unreach-call.i .62  5.5   41  
bitvector-regression/signextension_false-unreach-call.i .62  .59  49   4.2 2.4 170 .028 .033 5.1
bitvector-regression/implicitunsignedconversion_true-unreach-call.i .60  5.4   40  
bitvector-regression/integerpromotion_true-unreach-call.i .62  5.4   40  
bitvector-regression/signextension2_true-unreach-call.i .74  .72  51  
bitvector-regression/signextension_true-unreach-call.i .83  .87  50  
bitvector-loops/diamond_false-unreach-call2.i .56  5.4   41  
bitvector-loops/overflow_false-unreach-call1.i .64  .65  50   3.2 1.9 150 .029 .031 5.0
bitvector-loops/verisec_sendmail__tTflag_arr_one_loop_false-unreach-call.i .058 .070 2.6
../../sv-benchmarks/c/ status cputime (s) walltime (s) memUsage (MB) witness wit1_status wit1_cputime (s) wit1_walltime (s) wit1_memUsage (MB) wit2_status wit2_cputime (s) wit2_walltime (s) wit2_memUsage (MB)
total tasks 48 100   250   2600 48 11   6.4 490   48 .085 .097 15  
local summary 190  
    correct results 8 8.9 8.2 500 0 0   0   0   0 0     0     0  
        correct true 8 8.9 8.2 500 0 0   0   0   0 0     0     0  
        correct false 0
    incorrect results 0
        incorrect true 0
        incorrect false 0
score (48 tasks, max score: 84) 16
Run set sv-comp16