Tool CPAchecker 1.4-svcomp16c
Limits timelimit: 900 s, memlimit: 15000 MB, CPU core limit: 8
Host [zeus01; zeus02; zeus03; zeus04; zeus05; zeus06; zeus07; zeus08; zeus09; zeus10; zeus11; zeus12; zeus13; zeus14; zeus15; zeus16; zeus17; zeus18; zeus19; zeus20; zeus21; zeus22; zeus23; zeus24]
OS Linux 4.2.0-22-generic
System CPU: Intel Xeon E5-2650 v2 @ 2.60 GHz, cores: 32, frequency: 3.4 GHz; RAM: 135149 MB
Date of execution 2016-01-04 13:17:38 CET [[ 2016-01-15 08:48:20 CET ]] [[ 2016-01-15 22:10:37 CET ]]
Run set sv-comp16.BitVectorsReach
Options -sv-comp16 -disable-java-assertions -heap 10000m -setprop cpa.arg.errorPath.graphml=error-witness.graphml [[ -witness-check -disable-java-assertions -heap 10000m -setprop cpa.arg.errorPath.graphml=error-witness.graphml -spec ../../results-verified/cpa-seq.2016-01-04_1317.logfiles/sv-comp16.${inputfile_name}.files/error-witness.graphml ]][[ ../../results-verified/cpa-seq.2016-01-04_1317.logfiles/sv-comp16.${inputfile_name}.files/error-witness.graphml ]]
../../sv-benchmarks/c/ status cputime (s) walltime (s) memUsage (MB) witness wit1_status wit1_cputime (s) wit1_walltime (s) wit1_memUsage (MB) wit2_status wit2_cputime (s) wit2_walltime (s) wit2_memUsage (MB)
bitvector/byte_add_false-unreach-call.i false(reach) 87   57   3700 wit false(reach) 8.9 4.9 380 false(reach) 70   41   540
bitvector/byte_add_1_true-unreach-call.i true 38   17   1500 wit - -
bitvector/byte_add_2_true-unreach-call.i true 92   60   3800 wit - -
bitvector/gcd_1_true-unreach-call.i true 21   4.7 790 wit - -
bitvector/gcd_2_true-unreach-call.i true 270   110   3000 wit - -
bitvector/gcd_3_true-unreach-call.i true 280   120   2800 wit - -
bitvector/gcd_4_true-unreach-call.i true 2.9 1.3 180 wit - -
bitvector/interleave_bits_true-unreach-call.i true 22   5.2 700 wit - -
bitvector/jain_1_true-unreach-call.i true 310   130   6200 wit - -
bitvector/jain_2_true-unreach-call.i true 310   130   6000 wit - -
bitvector/jain_4_true-unreach-call.i true 310   140   7000 wit - -
bitvector/jain_5_true-unreach-call.i timeout 900   710   5500 wit - -
bitvector/jain_6_true-unreach-call.i true 310   130   7000 wit - -
bitvector/jain_7_true-unreach-call.i true 310   130   5500 wit - -
bitvector/modulus_true-unreach-call.i true 46   19   3700 wit - -
bitvector/num_conversion_1_true-unreach-call.i true 3.3 1.5 190 wit - -
bitvector/num_conversion_2_true-unreach-call.i true 13   3.8 660 wit - -
bitvector/parity_true-unreach-call.i true 67   15   1000 wit - -
bitvector/sum02_true-unreach-call.i timeout 900   710   4900 wit - -
bitvector/s3_clnt_1_false-unreach-call.BV.c.cil.c false(reach) 13   3.9 660 wit false(reach) 13   6.8 490 false(reach) 38   23   530
bitvector/s3_clnt_2_false-unreach-call.BV.c.cil.c false(reach) 17   5.7 710 wit false(reach) 14   7.5 480 false(reach) 41   23   550
bitvector/s3_clnt_3_false-unreach-call.BV.c.cil.c false(reach) 9.9 2.9 390 wit false(reach) 13   6.7 460 unknown 34   22   500
bitvector/s3_clnt_1_true-unreach-call.BV.c.cil.c true 28   18   1200 wit - -
bitvector/s3_clnt_2_true-unreach-call.BV.c.cil.c true 27   17   1300 wit - -
bitvector/s3_clnt_3_true-unreach-call.BV.c.cil.c true 30   19   1500 wit - -
bitvector/s3_srvr_1_alt_true-unreach-call.BV.c.cil.c timeout 900   700   3900 wit - -
bitvector/s3_srvr_1_true-unreach-call.BV.c.cil.c true 38   24   2400 wit - -
bitvector/s3_srvr_2_alt_true-unreach-call.BV.c.cil.c true 100   82   3700 wit - -
bitvector/s3_srvr_2_true-unreach-call.BV.c.cil.c true 100   82   3600 wit - -
bitvector/s3_srvr_3_alt_true-unreach-call.BV.c.cil.c true 35   23   2300 wit - -
bitvector/s3_srvr_3_true-unreach-call.BV.c.cil.c true 34   23   2300 wit - -
bitvector/soft_float_1_true-unreach-call.c.cil.c true 320   130   4300 wit - -
bitvector/soft_float_2_true-unreach-call.c.cil.c true 21   5.2 610 wit - -
bitvector/soft_float_3_true-unreach-call.c.cil.c timeout 900   690   7600 wit - -
bitvector/soft_float_4_true-unreach-call.c.cil.c true 510   330   4100 wit - -
bitvector/soft_float_5_true-unreach-call.c.cil.c true 24   5.6 680 wit - -
bitvector-regression/implicitfloatconversion_false-unreach-call.i false(reach) 3.6 1.6 200 wit false(reach) 4.3 2.5 220 error 9.5 5.4 320
bitvector-regression/implicitunsignedconversion_false-unreach-call.i false(reach) 3.0 1.4 200 wit false(reach) 4.6 2.8 220 false(reach) 11   6.1 320
bitvector-regression/integerpromotion_false-unreach-call.i false(reach) 5.1 2.0 240 wit false(reach) 6.9 3.9 340 false(reach) 20   14   370
bitvector-regression/signextension2_false-unreach-call.i false(reach) 4.9 2.0 230 wit false(reach) 7.4 4.1 330 false(reach) 11   6.5 330
bitvector-regression/signextension_false-unreach-call.i false(reach) 4.3 1.7 240 wit false(reach) 7.2 4.0 340 false(reach) 11   9.0 330
bitvector-regression/implicitunsignedconversion_true-unreach-call.i true 3.0 1.4 180 wit - -
bitvector-regression/integerpromotion_true-unreach-call.i true 4.0 1.7 190 wit - -
bitvector-regression/signextension2_true-unreach-call.i true 3.2 1.4 190 wit - -
bitvector-regression/signextension_true-unreach-call.i true 3.7 1.7 190 wit - -
bitvector-loops/diamond_false-unreach-call2.i false(reach) 4.4 1.7 230 wit false(reach) 5.8 3.4 250 false(reach) 14   7.7 340
bitvector-loops/overflow_false-unreach-call1.i timeout 900   700   4900 wit - -
bitvector-loops/verisec_sendmail__tTflag_arr_one_loop_false-unreach-call.i false(reach) 26   8.7 1100 wit false(reach) 9.1 5.1 420 timeout 91   84   400
../../sv-benchmarks/c/ status cputime (s) walltime (s) memUsage (MB) witness wit1_status wit1_cputime (s) wit1_walltime (s) wit1_memUsage (MB) wit2_status wit2_cputime (s) wit2_walltime (s) wit2_memUsage (MB)
total tasks 48 8400 5400 110000 48 94   52   3900   48 350   240   4500  
    correct results 43 3900 1900 87000 11 94   52   3900   8 350   240   4500  
        correct true 32 3700 1800 79000 0 0   0   0   0 0   0   0  
        correct false 11 180 89 7900 11 94   52   3900   8 350   240   4500  
    incorrect results 0
        incorrect true 0
        incorrect false 0
score (48 tasks, max score: 84) 75
Run set sv-comp16.BitVectorsReach